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DAC088S085 Datasheet(PDF) 8 Page - Texas Instruments |
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DAC088S085 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 41 page DB15 DB0 SCLK DIN SYNC tSYNC tDS tDH tCL tCH 1 / fSCLK tSH 1 2 13 14 15 16 tSS 8 DAC088S085 SNAS424D – AUGUST 2007 – REVISED APRIL 2016 www.ti.com Product Folder Links: DAC088S085 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated (1) This parameter is specified by design or characterization and is not tested in production. 7.6 AC and Timing Requirements Test limits are specified to AOQL (Average Outgoing Quality Level). Typical values apply for TA = 25°C; minimum and maximum limits apply for TA = –40°C to 125°C, unless otherwise noted. MIN NOM MAX UNIT fSCLK SCLK frequency 40 30 MHz ts Output voltage settling time(1) 40h to C0h code change, RL = 2 kΩ, CL = 200 pF 3 4.5 µs SR Output Slew Rate 1 V/µs GI Glitch Impulse Code change from 80h to 7Fh 40 nV-sec DF Digital Feedthrough 0.5 nV-sec DC Digital Crosstalk 0.5 nV-sec CROSS DAC-to-DAC crosstalk 1 nV-sec MBW Multiplying bandwidth VREF1,2 = 2.5 V ± 2 VPP 360 kHz ONSD Output noise spectral density DAC Code = 80h, 10 kHz 40 nV/ √(Hz) ON Output noise BW = 30 kHz 14 µV tWU Wake-up time VA = 3 V 3 µs VA = 5 V 20 1/fSCLK SCLK cycle time 33 25 ns tCH SCLK high time 10 7 ns tCL SCLK low time 10 7 ns tSS SYNC set-up time before SCLK falling edge TA = 25°C 3 1/fSCLK – 3 ns TA = –40°C to 125°C 10 tDS Data set-up time before SCLK falling edge 2.5 1 ns tDH Data hold time after SCLK falling edge 2.5 1 ns tSH SYNC hold time after the 16th falling edge of SCLK TA = 25°C 0 1/fSCLK – 3 ns TA = –40°C to 125°C 3 tSYNC SYNC high time 15 5 ns Figure 1. Serial Timing Diagram |
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