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DP83820 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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DP83820 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 87 page 9 www.national.com 3.0 Functional Description DP83820 consists of a PCI bus interface, BIOS ROM and EEPROM interfaces, Receive and Transmit Data Buffer Managers, an 802.3 Media Access Controller (MAC), SRAM, and miscellaneous support logic. Figure 3-1 DP83820 Functional Block Diagram 3.1 DP83820 The DP83820 device is an enhanced version of the NSC MacPhyter MAC/BIU (Media Access Controller/Bus Interface Unit) which has been modified for 1000 Mb/s operation with additional buffering, higher bandwidth PCI bus implementation, and the Gigabit Media Independent Interface for 1000BASE-T phy support. The DP83820 supports an external 10/100/1000 physical layer device. DP83820 contains the following major design elements: — a PCI bus interface, — an EEPROM interface, for access to an NMC93C06 EEPROM, — a buffer management scheme that is simple, efficient and flexible, — separate receive and transmit FIFOs and DMA controllers, — a 10/100/1000 Mb/s Ethernet Media Access Control (MAC), — a Physical Layer Interface (MII/GMII/TBI), — Management Information Base (MIB) Statistics Registers, — Receive Packet filtering logic. This following section provides a functional overview of interfaces of the DP83820. Rx Filter Tx Buffer Manager Rx Buffer Manager MIB Tx MAC Rx MAC PCI Bus Interface Data FIFO Data FIFO 93C06 Serial EEPROM DP83820 32 15 64 32 64 32 32 64 64 64 8 8 64 Boot ROM/ Flash MII MGMT SRAM |
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