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DAC7551IDRNTG4 Datasheet(PDF) 6 Page - Texas Instruments |
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DAC7551IDRNTG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 22 page www.ti.com SERIAL WRITE OPERATION SCLK SYNC SDIN D15 D14 D13 D12 D11 D1 D0 D15 t8 t4 t3 t2 t1 t7 t6 t5 D0 t9 Input Word n Input Word n+1 Undefined D15 D14 D0 Input Word n t10 SDO CLR TIMING CHARACTERISTICS (1) (2) DAC7551 SLAS441E – MARCH 2005 – REVISED APRIL 2007 Figure 1. Serial Write Operation Timing Diagram All specifications at –40 °C to +105°C, V DD = 2.7V to 5.5V, and RL = 2kΩ to GND (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.6V 20 t1(3) SCLK cycle time ns VDD = 3.6V to 5.5V 20 VDD = 2.7V to 3.6V 6.5 t2 SCLK HIGH time ns VDD = 3.6V to 5.5V 6.5 VDD = 2.7V to 3.6V 6.5 t3 SCLK LOW time ns VDD = 3.6V to 5.5V 6.5 VDD = 2.7V to 3.6V 4 t4 SYNC falling edge to SCLK falling edge setup time ns VDD = 3.6V to 5.5V 4 VDD = 2.7V to 3.6V 3 t5 Data setup time ns VDD = 3.6V to 5.5V 3 VDD = 2.7V to 3.6V 3 t6 Data hold time ns VDD = 3.6V to 5.5V 3 VDD = 2.7V to 3.6V 0 t1– 10ns(4) t7 SCLK falling edge to SYNC rising edge ns VDD = 3.6V to 5.5V 0 t1– 10ns(4) VDD = 2.7V to 3.6V 20 t8 Minimum SYNC HIGH time ns VDD = 3.6V to 5.5V 20 VDD = 2.7V to 3.6V 10 t9 SCLK falling edge to SDO valid ns VDD = 3.6V to 5.5V 10 VDD = 2.7V to 3.6V 10 t10 CLR pulse width low ns VDD = 3.6V to 5.5V 10 (1) All input signals are specified with tR = tF = 1ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Figure 1, Serial Write Operation timing diagram. (3) Maximum SCLK frequency is 50MHz at VDD = 2.7V to 5.5V. (4) SCLK falling edge to SYNC rising edge time shold not exceed (t1– 10ns) in order to latch the correct data. 6 Submit Documentation Feedback |
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