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DP8238J Datasheet(PDF) 6 Page - Texas Instruments |
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DP8238J Datasheet(HTML) 6 Page - Texas Instruments |
6 / 8 page Functional Pin Definitions (Continued) tion between the CPU memory and inputoutput devices for instructions and data transfers A status word (which de- scribes the current machine cycle) is also outputted on this data bus during the first microcycle of each machine cycle (SYNC e logic 1) System Data (DB7–DB0) Bus This bus comprises eight TRI-STATE inputoutput lines that connect to the memory and inputoutput components of the system The internal bidirectional bus driver isolates the DB7–DB0 Data Bus from the D7–D0 Data Bus Status Word Chart Machine Cycle Status Data Bus Bit Control Word D7 D6 D5 D4 D3 D2 D1 D0 Signal Instruction Fetch 1 1 0 1 0 0 0 1 0 MEMR Memory Read 2 1 0 0 0 0 0 1 0 MEMR Memory Write 3 0 0 0 0 0 0 0 0 MEMW Stack Read 4 1 0 0 0 0 1 1 0 MEMR Stack Write 5 0 0 0 0 0 1 0 0 MEMW Input Read 6 0 1 0 0 0 0 1 0 IOR Output Write 7 0 0 0 1 0 0 0 0 IOW Interrupt Acknowledge 8 0 0 1 0 0 0 1 1 INTA Halt Acknowledge 9 1 0 0 0 1 0 1 0 (none) Interrupt Acknowledge While Halt 10 0 0 1 0 1 0 1 1 INTA Block and Connection Diagrams TLF6825 – 6 Dual-In-Line Package TLF6825 – 7 Order Number DP8228J DP8228MJ DP8228N DP8238J DP8238MJ or DP8238N See NS Package Number J28A or N28B 5 |
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