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DP83815 Datasheet(PDF) 4 Page - Texas Instruments

Part # DP83815
Description  10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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DP83815 Datasheet(HTML) 4 Page - Texas Instruments

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5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . . 81
5.1.3 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . 82
5.1.4 Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2 Transmit Architecture . . . . . . . . . . . . . . . 83
5.2.1 Transmit State Machine . . . . . . . . . . . . . . . . . . . . . 83
5.2.2 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3 Receive Architecture . . . . . . . . . . . . . . . . 86
5.3.1 Receive State Machine . . . . . . . . . . . . . . . . . . . . . 86
5.3.2 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.0
Power Management and Wake-On-LAN. . 89
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 Definitions (for this document only) . . . . . 89
6.3 Packet Filtering . . . . . . . . . . . . . . . . . . . . 89
6.4 Power Management . . . . . . . . . . . . . . . . 89
6.4.1 D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.2 D1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.3 D2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.4 D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.5 D3cold State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.5 Wake-On-LAN (WOL) Mode . . . . . . . . . . 90
6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 90
6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.5.3 Exiting WOL Mode . . . . . . . . . . . . . . . . . . . . . . . . 91
6.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 91
6.6.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . 91
6.6.2 Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . 91
6.7 Pin Configuration for Power Management 91
7.0
DC and AC Specifications . . . . . . . . . . . . . 92
7.1 DC Specifications . . . . . . . . . . . . . . . . . . . 92
7.2 AC Specifications . . . . . . . . . . . . . . . . . . . 93
7.2.1 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 X1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.3 Power On Reset (PCI Active) . . . . . . . . . . . . . . . . 94
7.2.4 Non Power On Reset . . . . . . . . . . . . . . . . . . . . . . 94
7.2.5 POR PCI Inactive . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.6 PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.7 EEPROM Auto-Load . . . . . . . . . . . . . . . . . . . . . 101
7.2.8 Boot PROM/FLASH . . . . . . . . . . . . . . . . . . . . . . 102
7.2.9 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . 103
7.2.10 10BASE-T Transmit End of Packet . . . . . . . . . 104
7.2.11 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . 104
7.2.12 10BASE-T Normal Link Pulse . . . . . . . . . . . . . 105
7.2.13 Auto-Negotiation Fast Link Pulse (FLP) . . . . . . 105
7.2.14 Media Independent Interface (MII) . . . . . . . . . . 106
List of Figures
Figure 3-1
DP83815 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3-2
MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3-3
Ethernet Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3-4
DSP Physical Layer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-5
LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3-6
100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3-7
Binary to MLT-3 conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3-8
100 M/bs Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3-9
100BASE-TX BLW Event Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3-10
EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable . . . . . . . 26
Figure 3-11
MLT-3 Signal Measured at AII after 0 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3-12
MLT-3 Signal Measured at AII after 50 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3-13
MLT-3 Signal Measured at AII after 100 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3-14
10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3-15
Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 3-16
Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4-1
Pattern Buffer Memory - 180h words (word = 18bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 4-2
Hash Table Memory - 40h bytes addressed on word boundaries . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 5-1
Single Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 5-2
Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 5-3
List and Ring Descriptor Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 5-4
Transmit Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 5-5
Transmit State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 5-6
Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 5-7
Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
List of Tables
Table 3-1
4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 3-2
Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 4-1
Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 4-2
Operational Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 4-3
MIB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 5-1
DP83815 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 5-2
cmdsts Common Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 5-3
Transmit Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 5-4
Receive Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 5-5
Transmit State Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 5-6
Receive State Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 6-1
Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 6-2
PM Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91


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