Electronic Components Datasheet Search |
|
DAC7750IRHAT Datasheet(PDF) 10 Page - Texas Instruments |
|
|
DAC7750IRHAT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 53 page SCLK LATCH DIN SDO 1 1 8 2 2 9 24 24 23 22 DB23 DB23 DB0 DB0 DB0 DB16 t 12 t 17 t 16 t 13 t 14 t 15 t 18 t 20 t 19 t 11 Input word specifies register to be read Undefined data NOP condition X X X X First eight bits are bits don’t care Selected register data clocked out SCLK LATCH DIN 1 2 24 DB23 DB0 t 2 t 7 t 6 t 3 t 4 t 5 t 8 t 9 t 1 IOUT t 10 CLR 10 DAC7750, DAC8750 SBAS538B – DECEMBER 2013 – REVISED JUNE 2016 www.ti.com Product Folder Links: DAC7750 DAC8750 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated (1) Specified by design, not production tested. 7.9 Timing Requirements: Daisy-Chain Mode at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted) (1) MIN MAX UNIT t21 SCLK cycle time 60 ns t22 SCLK low time 25 ns t23 SCLK high time 25 ns t24 LATCH delay time 13 ns t25 LATCH high time 40 ns t26 Data setup time 5 ns t27 Data hold time 7 ns t28 LATCH low time 40 ns t29 Serial output delay time (CL, SDO = 15 pF) 35 ns Figure 1. Write Mode Timing Figure 2. Readback Mode Timing |
Similar Part No. - DAC7750IRHAT |
|
Similar Description - DAC7750IRHAT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |