CD74HC646M datasheet(6/14 Pages) TI1

Part #	CD74HC646M

Description	High-Speed CMOS Logic Octal Bus Transceiver/Register, Three-State

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6

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 2. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 4. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE:

Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL =1kΩ to

VCC, CL = 50pF.

FIGURE 5. HC THREE-STATE PROPAGATION DELAY TEST CIRCUIT

CLOCK

90%

50%

10%

GND

VCC

trCL

tfCL

50%

tWL

tWH

10%

tWL + tWH =

fCL

I

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

trCL

tfCL

GND

VCC

GND

VCC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

VCC

50%

90%

10%

50%

90%

tREM

tPLH

tSU(H)

tTLH

tTHL

tH(L)

tPHL

IC

CL

50pF

tSU(L)

tH(H)

50%

10%

90%

GND

VCC

10%

90%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

tPZH

tPHZ

tPZL

tPLZ

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZH

OUTPUT

RL = 1kΩ

CL

50pF

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