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DP83847ALQA56A Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP83847ALQA56A Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 60 page  5 www.national.com 1.0 Pin Descriptions The DP83847 pins are classified into the following interface categories (each interface is described in the sections that follow): — MII Interface — 10/100 Mb/s PMD Interface — Clock Interface — Special Connect Pins — LED Interface — Strapping Options/Dual Function pins —Reset — Power and Ground pins Note: Strapping pin option (BOLD) Please see Section 1.6 for strap definitions. All DP83847 signal pins are I/O cells regardless of the par- ticular use. Below definitions define the functionality of the I/O cells for each pin. 1.1 MII Interface Type: I Inputs Type: O Outputs Type: I/O Input/Output Type OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S Strapping Pin (All strap pins except PHY- AD[0:4] have internal pull-ups or pull- downs. If the default strap value is needed to be changed then an external 5 k Ω resistor should be used. Please see Table 1.6 on page 8 for details.) Signal Name Type LLP Pin # Description MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O, OD 24 MANAGEMENT DATA I/O: Bi-directional management instruc- tion/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 k Ω pullup resistor. CRS/LED_CFG O, S 45 CARRIER SENSE: Asserted high to indicate the presence of car- rier due to receive or transmit activity in 10BASE-T or 100BASE- TX Half Duplex Modes, while in full duplex mode carrier sense is asserted to indicate the presence of carrier due only to receive ac- tivity. COL O 43 COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with Heartbeat enabled this pin are also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test). In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig- nal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. TX_CLK O 36 TRANSMIT CLOCK: 25 MHz Transmit clock outputs in 100BASE-TX mode or 2.5 MHz in 10BASE-T mode derived from the 25 MHz reference clock. TXD[3] TXD[2] TXD[1] TXD[0]] I 41, 40, 39, 38 TRANSMIT DATA: Transmit data MII input pins that accept nib- ble data synchronous to the TX_CLK (2.5 MHz in 10BASE-T Mode or 25 MHz in 100BASE-TX mode). TX_EN I 37 TRANSMIT ENABLE: Active high input indicates the presence of valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10 Mb/s nibble mode. TX_ER I 35 TRANSMIT ERROR: In 100MB/s mode, when this signal is high and the corresponding TX_EN is active the HALT symbol is sub- stituted for data. In 10 Mb/s this input is ignored. RX_CLK O, PU 32 RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble mode. |
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