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DP83847ALQA56A Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP83847ALQA56A Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 60 page 7 www.national.com 1.3 Clock Interface 1.4 Special Connections 1.5 LED Interface Signal Name Type LLP Pin # Description X1 I 49 REFERENCE CLOCK INPUT 25 MHz: This pin is the primary clock reference input for the DP83847 and must be connected to a 25 MHz 0.005% ( ±50 ppm) clock source. The DP83847 sup- ports CMOS-level oscillator sources. X2 O 48 REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary clock reference output. Signal Name Type LLP Pin # Description RBIAS I 3 Bias Resistor Connection. A 10.0 k Ω 1% resistor should be con- nected from RBIAS to GND. C1 O 42 Reference Bypass Regulator. Parallel caps, 10 µ F (Tantalum pre- ferred) and .1 µF, should be placed close to C1 and connected to GND. See Section 3.8 for proper placement. RESERVED I/O 1, 2, 4, 5, 8, 9, 12, 13, 34, 44, 47, 50, 51, 52, 53, 54, 55, 61 RESERVED: These pins must be left unconnected Signal Name Type LLP Pin # Description LED_DPLX/PHYAD0 S, O 23 FULL DUPLEX LED STATUS: Indicates Full-Duplex status. LED_COL/PHYAD1 S, O 22 COLLISION LED STATUS: Indicates Collision activity in Half Du- plex mode. LED_GDLNK/PHYAD2 S, O 21 GOOD LINK LED STATUS: Indicates Good Link Status for 10BASE-T and 100BASE-TX. LED_TX/PHYAD3 S, O 20 TRANSMIT LED STATUS: Indicates transmit activity. LED is on for activity, off for no activity. LED_RX/PHYAD4 S, O 19 RECEIVE LED STATUS: Indicates receive activity. LED is on for activity, off for no activity. LED_SPEED O 18 SPEED LED STATUS: Indicates link speed; high for 100 Mb/s, low for 10 Mb/s. |
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