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CDC3RL02BYFPR Datasheet(PDF) 5 Page - Texas Instruments |
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CDC3RL02BYFPR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 20 page CDC3RL02 www.ti.com SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016 7.4 Thermal Information CDC3RL02 THERMAL METRIC(1) YFP (TSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 107.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 1.3 °C/W RθJB Junction-to-board thermal resistance 18.1 °C/W ψJT Junction-to-top characterization parameter 4.5 °C/W ψJB Junction-to-board characterization parameter 18.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LDO VOUT LDO output voltage IOUT = 50 mA 1.71 1.8 1.89 V CLDO External load capacitance 1 10 μF IOUT(SC) Short circuit output current RL = 0 Ω 100 mA IOUT(PK) Peak output current VBATT = 2.3 V, VLDO = VOUT – 5% 100 mA fIN= 217 Hz and 1 kHz 60 PSR Power supply rejection VBATT = 2.3 V, IOUT = 2 mA, dB fIN= 3.25 MHz 40 VBATT = 2.3 V , CLDO = 1 μF, 0.2 CLK_REQ_n to VLDO = 1.71 V tsu LDO startup time ms VBATT = 5.5 V , CLDO = 10 μF, 1 CLK_REQ_n to VLDO = 1.71 V POWER CONSUMPTION ISB Standby current Device in standby (all VCLK_REQ_n = 0 V) 0.2 1 μA ICCS Static current consumption Device active but not switching 0.4 1 mA IOB Output buffer average current fIN = 26 MHz, CLOAD = 50 pF 4.2 mA Output power dissipation CPD fIN = 26 MHz 44 pF capacitance MCLK_IN INPUT MCLK_IN, CLK_REQ_1/2 leakage II VI = VLDO or GND 1 μA current CI MCLK_IN capacitance fIN = 26 MHz 4.75 pF RI MCLK_IN impedance fIN = 26 MHz 6 k Ω fIN MCLK_IN frequency range 10 26 52 MHz MCLK_IN LVCMOS SOURCE 1-kHz offset –140 10-kHz offset –149 Additive phase noise fIN = 26 MHz, tr/tf ≤ 1 ns dBc/Hz 100-kHz offset –153 1-MHz offset –148 Additive jitter fIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz 0.37 ps (rms) MCLK_IN to CLK_OUT_n tDL 11 ns propagation delay DCL Output duty cycle fIN = 26 MHz, DCIN = 50% 45% 50% 55% Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: CDC3RL02 |
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