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CDC319 Datasheet(PDF) 2 Page - Texas Instruments |
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CDC319 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS OUTPUTS OE A 1Y0–1Y3 2Y0–2Y3 3Y0–3Y1 L X Hi-Z Hi-Z Hi-Z H L L L L H H H† H† H† † The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input. logic diagram (positive logic) 1Y0–1Y3 2Y0–2Y3 3Y0 – 3Y1 OE SDATA SCLOCK A I2C Register Space I2C 20 14 15 9 2, 3, 6, 7 22, 23, 26, 27 11, 18 10 / Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 1Y0–1Y3 2, 3, 6, 7 O 3.3-V SDRAM byte 0 clock outputs 2Y0–2Y3 22, 23, 26, 27 O 3.3-V SDRAM byte 1 clock outputs 3Y0–3Y1 11, 18 O 3.3-V clock outputs provided for feedback control of external PLLs (phase-locked loops) A 9 I Clock input OE 20 I Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal 140-k Ω pullup resistor is internally integrated. SCLOCK 15 I I2C serial clock input. A nominal 140-k Ω pullup resistor is internally integrated. SDATA 14 I/O Bidirectional I2C serial data input/output. A nominal 140-k Ω pullup resistor is internally integrated. GND 4, 8, 12, 16, 17, 21, 25 Ground VCC 1, 5, 10, 13, 19, 24, 28 3.3-V power supply |
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