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ACD2206 Datasheet(PDF) 8 Page - ANADIGICS, Inc |
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ACD2206 Datasheet(HTML) 8 Page - ANADIGICS, Inc |
8 / 20 page 8 PRELIMINARY DATA SHEET - Rev 1.0 10/2003 ACD2206 T C E L E S S T I B R O F R E T S I G E R N O I T A N I T S E D A T A D L A I R E S S 2 S 1 00 2 L L P r o f r e t s i g e R r e d iv i D e c n e r e f e R 01 2 L L P r o f r e t s i g e R r e d iv i D n i a M 10 1 L L P r o f r e t s i g e R r e d iv i D e c n e r e f e R 11 1 L L P r o f r e t s i g e R r e d i v i D n i a M E D I V I D R O I T A R R 5 1 R 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 3 0000000 0 00000 1 1 4 0000000 0 0000 1 0 0 - ------- - ------ - 7 6 7 2 3 1111111 1 111111 1 2 2 1 2 0 2 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 8 7 6 5 4 3 2 1 e d o M m a r g o r PR , o it a R e d i v i D r e d i v i D e c n e r e f e Rt c e l e S D 5 D 4 D 3 D 2 D 1 R 5 1 R 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 S 2 S 1 LOGIC PROGRAMMING Notes: Divide ratios less than 3 are prohibited. LSB MSB Synthesizer Register Programming The ACD2206 includes two PLL synthesizers. Each synthesizer contains programmable Reference and Main dividers, which allow a wide range of local oscillator frequencies. The 22-bit registers that control the dividers are programmed via a shared three-wire bus, consisting of Data, Clock and Enable lines. The data word for each register is entered serially in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The rising edge of the Clock pulse shifts each data value into the register. The Enable line must be low for the duration of the data entry, then set high to latch the data into the register. (See Figure 4.) Register Select Bits The two least significant bits of each register are register select bits that determine which register is programmed during a particular data entry cycle. Table 7 indicates the register select bit settings used to program each of the available registers. Table 7: Register Select Bits Table 9: Reference Divider R Counter Bits Table 8: Reference Divider Registers Reference Divider Programming The reference divider register for each synthesizer consists of fifteen divider bits, five program mode bits and the two register select bits, as shown in Table 8. The fifteen divider bits allow a divide ratio from 3 to 32767, inclusive, as shown in Table 9. |
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Similar Description - ACD2206 |
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