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DRV593VFP Datasheet(PDF) 11 Page - Texas Instruments |
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DRV593VFP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 27 page V Load + D V DD D + Av VIN)–VIN– V DD H/C PWM Load Voltage VDD VDD VDD VDD/2 0 0 0 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 APPLICATION INFORMATION PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594 The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full output filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and capacitor for the output filter. The H/C outputs determine the direction of the current and do not switch back and forth. The PWM outputs switch to produce a voltage across the load that is proportional to the input control voltage. COOLING MODE Figure 18 shows the DRV593 and DRV594 in cooling mode. The H/C outputs (pins 14-17) are at ground and the PWM outputs (pins 24-27) create a voltage across the load that is proportional to the input voltage. The differential voltage across the load is determined using Equation 1 and the duty cycle using Equation 2. The differential voltage is defined as the voltage measured after the filter on the PWM output relative to the H/C output. (1) (2) where D duty cycle of the PWM signal Av Gain of DRV593/594 (DRV593: 2.3 V/V, DRV594: 14.5 V/V) VIN+ Positive input terminal of the DRV593/594 VIN– Negative input terminal of the DRV593/594 VDD Power supply voltage For example, a 50% duty cycle, shown in Figure 18, results in 2.5 V across the load for VDD = 5 V. Figure 18. Cooling Mode Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): DRV593 DRV594 |
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