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DS100DF410SQ Datasheet(PDF) 10 Page - Texas Instruments |
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DS100DF410SQ Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 57 page  0 1 2 3 4 5 6 7 8 9 10 -1.0 -0.5 0.0 0.5 1.0 TIME (UI) DS100DF410 SNLS399B – JANUARY 2012 – REVISED JANUARY 2015 www.ti.com Feature Description (continued) 7.3.3 CTLE The CTLE in the DS125DF410 is a fully adaptive equalizer with optional limiting stage. The CTLE adapts according to a Figure of Merit (FOM) calculation during the lock acquisition process. Once the CDR has locked and the CTLE has been adapted, the CTLE boost level will be frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE is typically readapted by resetting the CDR. The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost settings. CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost combinations that sum to the same number will have approximately the same boost level, but will result in a different shape for the EQ transfer function (boost curve). The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather than a linear stage. This is useful in some applications, but it should not be typically used in combination with the DFE. 7.3.4 DFE A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the selected adapt mode. The DFE can be manually configured to specified tap polarities and tap weights. The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity bit. 7.3.5 Clock and Data Recovery The DS100DF410 performs its clock and data recovery function by detecting the bit transitions in the incoming data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit transitions. This process produces a recovered clock with jitter which is greatly reduced for jitter frequencies outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS100DF410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system. 7.3.6 Output Driver The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis. The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The DS100DF410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user is responsible for configuring these parameters. They can be set for each channel independently. An idealized transmit waveform with analog de-emphasis applied is shown in Figure 4. Figure 4. Idealized De-Emphasis Waveform 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS100DF410 |
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