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DS125BR401A Datasheet(PDF) 10 Page - Texas Instruments |
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DS125BR401A Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 52 page  IN 0V tPLHD OUT 0V tPHLD + - + - 0V 20% 80% 20% 80% tFALL tRISE VOD = [Out+ - Out-] DS125BR401A SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014 www.ti.com 6.6 Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data, Clock Input Low Voltage 0.8 V VIH Data, Clock Input High Voltage 2.1 3.6 V VOL Output Low Voltage SDA or SCL, IOL = 1.25 mA 0 0.36 V VDD Nominal Bus Voltage 2.375 3.6 V IIH-Terminal Input Leakage Per Device Terminal +20 +150 µA IIL-Terminal Input Leakage Per Device Terminal -160 -40 µA CI Capacitance for SDA and SCL See(1)(2) < 5 pF RTERM External Termination Resistance Pullup VDD = 3.3V (1) (2) (3) 2000 Ω pull to VDD = 2.5V ± 5% OR 3.3V ± Pullup VDD = 2.5V (1) (2) (3) 1000 Ω 10% (1) Recommended value. (2) Recommended maximum capacitance load per bus segment is 400pF. (3) Maximum termination voltage should be identical to the device supply voltage. 6.7 Timing Requirements Serial Bus Interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL BUS INTERFACE TIMING SPECIFICATIONS FSMB Bus Operating Frequency ENSMB = VDD (Slave Mode) 400 kHz ENSMB = FLOAT (Master Mode) 280 400 520 kHz tFALL SDA Fall Time Read operation 60 ns RPU = 4.7K, Cb < 50pF tRISE SDA Rise Time Read operation 140 ns RPU = 4.7K, Cb < 50pF tF Clock/Data Fall Time See(1) 300 ns tR Clock/Data Rise Time See(1) 1000 ns (1) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details. Figure 1. Output and Rise And Fall Transition Time Figure 2. Propagation Delay Timing Diagram 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: DS125BR401A |
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