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DS125BR820NJYR Datasheet(PDF) 10 Page - Texas Instruments |
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DS125BR820NJYR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 62 page  DS125BR820 SNLS491B – JULY 2014 – REVISED FEBRUARY 2015 www.ti.com Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Evaluation Module (EVM) Only, FR4, VID = 800 mVp-p, EQ = Level 1 RJADD Additive Random Jitter 0.36 ps rms PRBS15, 12 Gbps VOD = Level 6 All other channels active (4) EQUALIZATION 5” Differential Stripline, 5mil trace width, FR4, DJE1 Residual deterministic jitter at 6 Gbps VID = 800 mVp-p, 0.06 UIp-p PRBS15, EQ = Level 2, VOD = Level 6 5” Differential Stripline, 5mil trace width, FR4, Residual deterministic jitter at 12 DJE2 VID = 800 mVp-p, 0.12 UIp-p Gbps PRBS15, EQ = Level 2, VOD = Level 6 (4) Additive random jitter is given in RMS value by the following equation: RJADD = √[(Output Jitter) 2 - (Input Jitter)2]. Typical input jitter for these measurements is 150 fs rms. 6.6 Electrical Characteristics — Serial Bus Interface DC Specifications Over recommended operating supply and temperature ranges unless other specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Data, Clock Input Low Voltage 0.8 V VIH Data, Clock Input High Voltage 2.1 3.6 V VOL Output Low Voltage SDA or SCL, IOL = 1.25 mA 0 0.36 V VDD Nominal Bus Voltage 2.375 3.6 V IIH-Pin Input Leakage Per Device Pin +20 +150 µA IIL-Pin Input Leakage Per Device Pin -160 -40 µA CI Capacitance for SDA and SCL See(1)(2) < 5 pF External Termination Resistance Pullup VDD = 3.3 V (1) (2) (3) 2000 Ω RTERM pull to VDD = 2.5 V ± 5% OR 3.3 V Pullup VDD = 2.5 V (1) (2) (3) 1000 Ω ± 10% (1) Recommended value. (2) Recommended maximum capacitance load per bus segment is 400 pF. (3) Maximum termination voltage should be identical to the device supply voltage. 6.7 Serial Bus Interface Timing Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENSMB = VDD (Slave Mode) 400 kHz FSMB Bus Operating Frequency ENSMB = FLOAT (Master Mode) 280 400 520 kHz Read operation tFALL SCL or SDA Fall Time 60 ns RPU = 4.7 k Ω, Cb < 50 pF Read operation tRISE SCL or SDA Rise Time 140 ns RPU = 4.7 k Ω, Cb < 50 pF tF Clock/Data Fall Time See(1) 300 ns tR Clock/Data Rise Time See(1) 1000 ns Time in which a device must be tPOR See(1) 500 ms operational after power-on reset (1) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details. 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated |
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