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CDCV857DGGG4 Datasheet(PDF) 5 Page - Texas Instruments |
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CDCV857DGGG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 14 page CDCV857 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input voltage All inputs VDDQ = 2.3 V, II = –18 mA –1.2 V VOH High level output voltage VDDQ = min to max, IOH = –1 mA VDDQ– 0.1 V VOH High-level output voltage VDDQ = 2.3 V, IOH = –12 mA 1.7 V VOL Low level output voltage VDDQ = min to max, IOL = 1 mA 0.1 V VOL Low-level output voltage VDDQ = 2.3 V, IOL = 12 mA 0.6 V IOH High-level output current VDDQ = 2.3 V, VO = 1 V –18 –32 mA IOL Low-level output current VDDQ = 2.3 V, VO = 1.2 V 26 35 mA VO Output voltage swing Differential outputs are terminated with 1.1 VDDQ– 0.4 VOX Output differential cross-voltage w Differential outputs are terminated with 120 Ω VDDQ/2 – 0.2 VDDQ/2 VDDQ/2 + 0.2 V II Input current VDDQ = 2.7 V, VI = 0 V to 2.7 V ±10 µA IOZ High-impedance-state output current VDDQ = 2.7 V, VO= VDDQ or GND ±10 µA IDDPD Power down current on VDDQ + AVDD CLK and CLK = 0 MHz; PWRDWN = Low; Σ of IDD and AIDD 100 200 µA IDD Dynamic current on VDDQ all outputs loaded as shown in fO = 200 MHz 275 330 mA IDD Dynamic current on VDDQ as shown in Figure 3 fO = 167 MHz 250 300 mA AIDD Supply current on AVDD fO = 200 MHz 10 12 mA AIDD Supply current on AVDD fO = 167 MHz 8 10 mA CI Input capacitance VCC = 2.5 V VI = VCC or GND 2 2.5 3 pF CO Output capacitance VCC = 2.5 V VO = VCC or GND 2.5 3 3.5 pF † All typical values are at respective nominal VDDQ. ‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage. § Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT fCK Operating clock frequency 60 200 MHz fCK Application clock frequency 60 200 MHz Input clock duty cycle 40% 60% Stabilization time W (PLL mode) 10 µs Stabilization time W (Bypass mode) 30 ns ¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. |
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