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CDCVF310PWR Datasheet(PDF) 4 Page - Texas Instruments |
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CDCVF310PWR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 16 page www.ti.com DETAILED DESCRIPTION Output Enable Glitch Suppression Circuit CLK Gn Yn tsu(en) th(en) CLK Gn Yn tsu(dis) th(dis) a) Enable Mode b) Disable Mode CDCVF310 SCAS771B – AUGUST 2004 – REVISED JANUARY 2008 The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the input clock) (see Figure 1). The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable operation. Figure 1. Enable and Disable Mode Relative to CLK ↓ 4 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): CDCVF310 |
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