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CLC5903 Datasheet(PDF) 3 Page - Texas Instruments |
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CLC5903 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 31 page  www.national.com 2 Functional Description The CLC5903 block diagram is shown in Figure 2. The CLC5903 contains two identical digital down-conversion (DDC) circuits. Each DDC accepts an independently clocked 14-bit sample at up to 78MSPS, down conver ts from a selected carrier frequency to baseband, decimates the signal rate by a programmable factor ranging from 32 to 16384, pro- vides channel filtering, and outputs quadrature symbols. A crossbar switch enables either of the two inputs or a test register to be routed to either DDC channel. Flexible channel filtering is provided by the two programmable decimating FIR filters. The final filter outputs can be converted to a 12-bit floating point format or standard two’s complement format. The output data is available at both serial and parallel ports. The CLC5903 maintains over 100 dB of spurious free dynamic range and over 100 dB of out-of-band rejection. This allows considerable latitude in channel filter partitioning between the analog and digital domains. The frequencies, phase offsets, and phase dither of the two sine/cosine numerically controlled oscillators (NCOs) can be independently specified. Two sets of coefficient memories and a crossbar switch allow shared or independent filter coefficients and bandwidth for each channel. Both channels share the same decimation ratio and input/output formats. Each channel has its own AGC circuit for use with narrow- band radio channels where most of the channel filtering pre- cedes the ADC. The AGC closes the loop around the CLC5526 DVGA, compressing the dynamic range of the sig- nal into the ADC. AGC gain compensation in the CLC5903 removes the DVGA gain steps at the output. The time align- ment of this gain compensation circuit can be adjusted to support ADCs with different latencies. The AGC can be con- figured to operate continuously or set to a fixed gain step. The two AGC circuits operate independently but share the same programmed parameters and control signals. The chip receives configuration and control information over a microprocessor-compatible bus consisting of an 8-bit data I/O port, an 8-bit address port, a chip enable strobe, a read strobe, and a write strobe. The chip’s control registers (8 bits each) are memory mapped into the 8-bit address space of the control port. Page select bits allow access to the overlaid A and B set of FIR coefficients. JTAG boundary scan and on-chip diagnostic circuits are pro- vided to simplify system debug and test. The CLC5903 supports 3.3V I/O even though the core logic voltage is 1.8V. The CLC5903 outputs swing to the 3.3V rail so they can be directly connected to 5V TTL inputs if desired. Figure 2. CLC5903 Dual Digital Tuner / AGC Block Diagram with Control Register Associations AIN BIN MUX MUX Input Source Output Controls Output Formatter Floating Point: 32-bit Truncated or 24-bit Rounded or 16-bit Rounded or 8-bit Truncated Two’s Complement: 4-bit Exponent and 8-bit Mantissa or AOUT/BOUT BOUT SCK SFS RDY POUT[15..0] PSEL[2..0] POUT_EN A_SOURCE B_SOURCE RATE SOUT_EN SCK_POL SFS_POL RDY_POL MUX_MODE PACKED FORMAT DEBUG_EN DEBUG_TAP CKA CLK GEN TEST_REG Channel B Controls GAIN_B FREQ_B PHASE_B AGC_IC_B AGC_RB_B DITH_B Common Channel Controls DEC_BY_4 SCALE EXP_INH AGC_HOLD_IC AGC_LOOP_GAIN AGC_TABLE F1B_COEFF F2B_COEFF AGAIN[2..0] ASTROBE BGAIN[2..0] BSTROBE Microprocessor Interface RD WR CE A[7:0] D[7:0] SI MR Sync Logic 14 14 DEC A B Channel A Tuning, Channel Filters, and AGC (see Figure 16) Channel B Tuning, Channel Filters, and AGC (see Figure 16) (see Figure 29) SCK_IN SFS_MODE SDC_EN AGC_COMB_ORD EXT_DELAY COEF_SEL_F1B COEF_SEL_F2B Channel A Controls GAIN_A FREQ_A PHASE_A AGC_IC_A AGC_RB_A DITH_A COEF_SEL_F1A COEF_SEL_F2A F1A_COEFF F2A_COEFF PAGE_SEL_F1 PAGE_SEL_F2 CKB |
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