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DS125DF111 Datasheet(PDF) 7 Page - Texas Instruments |
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DS125DF111 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 54 page  DS125DF111 www.ti.com SNLS450A – JANUARY 2014 – REVISED JUNE 2015 6.5 Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT R_Baud Input baud rate (primary VCO range) Full Rate: DS125DF111 9.8 12.5 Gbps R_Baud2 Divide by 2 Half Rate: DS125DF111 4.9 6.25 Gbps R_Baud4 Divide by 4 Quarter Rate: DS125DF111 2.45 3.125 Gbps R_Baud8 Divide by 8 Eighth Rate: DS125DF111 1.225 1.5625 Gbps Slave Mode Clock Rate 100 400 FSDC SMBus Clock Rate kHz Master Mode Clock Rate 280 400 520 REFCLK Reference Clock Rate ± 100 ppm 25 MHz DCREFCLK Reference Clock Duty Cycle 40% 50% 60% POWER SUPPLY CURRENT Average Supply Current, Default Settings, CHA and CHB Locked 175 mA DFE Enabled Average Supply Current, CHA and CHB Locked DS125DF111 Current Consumption 155 mA IDD Default Settings except DFE (Whole Device) Disabled Maximum Transient Supply Current Default Settings: CHA and CHB 294 333 mA valid input signal detected CHA and CHB acquiring LOCK(2) 50 Hz to 100 Hz 100 mVp-p NTps Supply Noise Tolerance 100 Hz to 10 MHz 40 mVp-p 10 MHz to 3.0 GHz 10 mVp-p LVCMOS (ADDR[1:0], READEN#, REFCLK_IN, DONE#, LOCK) VIH High level input voltage 2.5 V or 3.3 V Supply Mode 1.7 VIN V VIL Low level input voltage 2.5 V or 3.3 V Supply Mode 0.7 VOH1 High level output voltage IOH = -3 mA 2 VIN VOH2 High level output voltage IOH = –100 µA VIN - 0.1 V VOL Low level output voltage IOL = 3 mA 0.4 IIN Input leakage current VINPUT = GND or VIN –15 15 µA 4-LEVEL INPUTS (ENSMB, DEMA, DEMB, LPBK, TX_DIS, VODA, VODB) IIH-R Input leakage current High VINPUT = VIN 80 µA IIL-R Input leakage current Low VINPUT = GND –160 µA OPEN DRAIN (LOS/INT#) VOL Low level output voltage IOL = 3 mA 0.4 V SIGNAL DETECT Signal Detect: Default level to assert SDH 18 mVp-p ON Threshold Level Signal Detect, 12.5 Gbps, PRBS31 Signal Detect: Default level to de-assert SDL 14 mVp-p OFF Threshold Level Signal Detect, 12.5 Gbps, PRBS31 CML RX INPUTS R_Rd DC Input differential Resistance 80 100 120 Ω SDD11 10 MHz –19 RLRX-IN Input Return-Loss SDD11 2.0 GHz –13 dB SDD11 6.0 - 11.1 GHz -8 VRX- Tx Launch amplitude of driver Source Transmit Signal Level 1600 mVp-p LAUNCH connected to DS125DF111 inputs(3) (1) Typical values represent the most likely parametric norm as determined at the time of design and characterization. Actual typical values may vary over time and will also depend on the application and configuration. (2) Peak current only occurs during lock acquisition, limit is for power supply design not needed for thermal calculations. (3) DS125DF111 equalizer is optimized to adapt to Tx Launch amplitudes between 600 - 1200 mV. Amplitudes above or below this range will reduce the overall equalizer performance. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS125DF111 |
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