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DP83848H Datasheet(PDF) 8 Page - Texas Instruments |
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DP83848H Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 84 page  DP83848H, DP83848J, DP83848K, DP83848M, DP83848T SNLS250E – MAY 2008 – REVISED APRIL 2015 www.ti.com 4.7 Reset SIGNAL TYPE PIN # DESCRIPTION NAME RESET: Active Low input that initializes or re-initializes the DP83848x. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their RESET_N I, PU 23 default states as specified for each bit in the Register Block section. All strap options are re- initialized as well. 4.8 Strap Options DP83848x uses many functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses. A 2.2-k Ω resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Because these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND. SIGNAL NAME TYPE PIN # DESCRIPTION PHY ADDRESS [4:0]: The DP83848x provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset. PHYAD0 (COL) 35 The DP83848x supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). PHYAD1 (RXD_0) 36 A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must S, O, PU PHYAD2 (RXD_1) 37 be selected by strapping Phy Address 0; changing to Address 0 by register write will not put S, O, PD PHYAD3 (RXD_2) 38 the Phy in the MII isolate mode. Refer to Section 6.4.4 for additional information. PHYAD4 (RXD_3) 39 PHYAD0 pin has weak internal pullup resistor. PHYAD[4:1] pins have weak internal pulldown resistors. These input pins control the advertised operating mode of the device according to the following table. The value on these pins are set by connecting them to GND (0) or VCC (1) through 2.2-k Ω resistors. These pins should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848x at Hardware-Reset. The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default for DP83848x is 11 because these pins have an internal pullup. AN0 (LED_LINK) S, O, PU 22 AN1 S, O, PU 21 AN1(1) AN0 Advertised Mode (LED_SPEED)(1) 0 0 10BASE-T, Half/full-Duplex 0 1 100BASE-TX, Half/full-Duplex 1 0 10BASE-T, Half-Duplex 100BASE-TX, Half-Duplex 1 1 10BASE-T, Half/Full-Duplex 100BASE-TX, Hal/Full-Duplex MII MODE SELECT: This strapping option determines the operating mode of the MAC Data Interface. Default operation (No pullup) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII mode of operation. Because the pin includes an internal pulldown, the default value is 0. The following table details the configuration: MII_MODE (RX_DV) S, O, PD 32 MIL_MODE MAC Interface Mode 0 MII Mode 1 RMII Mode LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap LED_CFG S, O, PU 33 option. All modes are configurable through register access. (CRS/CRS_DV) See Table 6-2 for LED Mode Selection. MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An MDIX_EN (RX_ER) S, O, PU 34 external pulldown will disable Auto-MDIX mode. (1) AN1 (LED_SPEED) is only available on the DP83848J/K. 8 Pin Configuration and Functions Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T |
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