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DP83849I Datasheet(PDF) 7 Page - Texas Instruments |
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DP83849I Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 98 page  DP83849I www.ti.com SNOSAX1F – MAY 2008 – REVISED SEPTEMBER 2015 3.2 Signal Descriptions 3.2.1 Serial Management Interface SIGNAL NAME TYPE PIN NO. DESCRIPTION MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5-k Ω pullup resistor. 3.2.2 Clock Interface SIGNAL NAME TYPE PIN NO. DESCRIPTION X1 I 70 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83849I and must be connected to a 25 MHz 0.005% (+50 ppm) clock source. The DP83849I supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50-MHz 0.005% (+50 ppm) CMOS-level oscillator source. X2 O 69 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. CLK2MAC O 68 CLOCK TO MAC: In MII mode, this pin provides a 25-MHz clock output to the system. In RMII mode, this pin provides a 50-MHz clock output to the system. This allows other devices to use the reference clock from the DP83849I without requiring additional clock sources. If the system does not require the CLK2MAC signal, the CLK2MAC output must be disabled through the CLK2MAC disable strap. 3.2.3 MAC Data Interface SIGNAL NAME TYPE PIN NO. DESCRIPTION TX_CLK_A 12 MII TRANSMIT CLOCK: 25-MHz Transmit clock output in 100-Mb/s mode or 2.5 MHz in 10-Mb/s mode derived from the 25-MHz reference clock. Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz O reference for both transmit and receive. TX_CLK_B 50 SNI TRANSMIT CLOCK: 10-MHz Transmit clock output in 10-Mb/s SNI mode. The MAC must source TX_EN and TXD_0 using this clock. TX_EN_A 13 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0]. RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on I TXD[1:0]. TX_EN_B 49 SNI TRANSMIT ENABLE: 10-MHz Transmit clock output in 10-Mb/s SNI mode. The MAC must source TX_EN and TXD_0 using this clock. TXD[3:0]_A 17, 16, 15, 14 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data I synchronous to the 50-MHz reference clock. TXD[3:0]_B 45, 46, 47, 48 SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode). MII RECEIVE CLOCK: Provides the 25-MHz recovered receive clocks for 100 Mb/s RX_CLK_A 79 mode and 2.5 MHz for 10 Mb/s mode. Unused in RMII mode. The device uses the X1 reference clock input as the 50-MHz O reference for both transmit and receive. RX_CLK_B 63 SNI RECEIVE CLOCK: Provides the 10-MHz recovered receive clocks for 10 Mb/s SNI mode. Copyright © 2008–2015, Texas Instruments Incorporated Terminal Configuration and Functions 7 Submit Documentation Feedback Product Folder Links: DP83849I |
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