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BQ34Z651DBTR Datasheet(PDF) 9 Page - Texas Instruments |
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BQ34Z651DBTR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 29 page  bq34z651 www.ti.com SLUSAL7 – AUGUST 2011 ELECTRICAL CHARACTERISTICS (continued) Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LED OUTPUTS VOL Output low voltage LED1, LED2, LED3, LED4, LED5 0.4 V VCELL+ HIGH VOLTAGE TRANSLATION VC(n) – VC(n+1) = 0 V; 0.950 0.975 1 TA = –40°C to 100°C V(VCELL+OUT) VC(n) – VC(n+1) = 4.5 V; 0.275 0.3 0.375 TA = –40°C to 100°C Internal AFE reference voltage; V(VCELL+REF) Translation output 0.965 0.975 0.985 V TA = –40°C to 100°C Voltage at PACK pin; 0.98 × 1.02 × V(VCELL+PACK) V(PACK)/18 TA = –40°C to 100°C V(PACK)/18 V(PACK)/18 Voltage at BAT pin; 0.98 × 1.02 × V(VCELL+BAT) V(BAT)/18 TA = –40°C to 100°C V(BAT)/18 V(BAT)/18 CMMR Common mode rejection ratio VCELL+ 40 dB K= {VCELL+ output (VC5=0 V; VC4=4.5 V) – VCELL+ output (VC5 = 0 V; VC4 =0 0.147 0.150 0.153 V)}/4.5 K Cell scale factor K= {VCELL+ output (VC2 = 13.5 V; VC1 = 18 V) – VCELL+ output 0.147 0.150 0.153 (VC5 = 13.5 V; VC1 = 13.5 V)}/4.5 VC(n) – VC(n+1) = 0 V; VCELL+ = 0 V; I(VCELL+OUT) Drive Current to VCELL+ capacitor 12 18 μA TA = –40°C to 100°C CELL output (VC2 = VC1 = 18 V) – CELL V(VCELL+O) CELL offset error –18 –1 18 mV output (VC2 = VC1 = 0 V) IVCnL VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V –1 0.01 1 μA CELL BALANCING RDS(on) for internal FET switch at RBAL Internal cell balancing FET resistance 200 400 600 Ω VDS = 2 V; TA = 25°C HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted) VOL = 25 mV (min) 15 25 35 OL detection threshold voltage V(OL) VOL = 100 mV; RSNS = 0, 1 90 100 110 mV accuracy VOL = 205 mV (max) 185 205 225 V(SCC) = 50 mV (min) 30 50 70 SCC detection threshold voltage V(SCC) V(SCC) = 200 mV; RSNS = 0, 1 180 200 220 mV accuracy V(SCC) = 475 mV (max) 428 475 523 V(SCD) = –50 mV (min) –30 –50 –70 SCD detection threshold voltage V(SCD) V(SCD) = –200 mV; RSNS = 0, 1 –180 –200 –220 mV accuracy V(SCD) = –475 mV (max) –428 –475 –523 tda Delay time accuracy ±15.25 μs tpd Protection circuit propagation delay 50 μs FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted) V(DSGON) = V(DSG) – V(PACK); V(DSGON) DSG pin output on voltage V(GS) = 10 MΩ; DSG and CHG on; 8 12 16 V TA = –40°C to 100°C V(CHGON) = V(CHG) – V(BAT); V(CHGON) CHG pin output on voltage V(GS) = 10 MΩ; DSG and CHG on; 8 12 16 V TA = –40°C to 100°C V(DSGOFF) DSG pin output off voltage V(DSGOFF) = V(DSG) – V(PACK) 0.2 V V(CHGOFF) CHG pin output off voltage V(CHGOFF) = V(CHG) –V(BAT) 0.2 V CL= 4700 pF; V(PACK) ≤ DSG ≤ V(PACK) + 400 1000 4 V tr Rise time μs CL= 4700 pF; V(BAT) ≤ CHG ≤ V(BAT) + 4 V 400 1000 CL= 4700 pF; V(PACK) + V(DSGON) ≤ DSG ≤ 40 200 V(PACK) + 1 V tf Fall time μs CL= 4700 pF; V(BAT) + V(CHGON) ≤ CHG ≤ 40 200 V(BAT) + 1 V Copyright © 2011, Texas Instruments Incorporated 9 |
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