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BQ4845YS-A4G4 Datasheet(PDF) 5 Page - Texas Instruments |
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BQ4845YS-A4G4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 24 page the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CS and OE remain low, output data remains valid for tOH (output data hold time), but goes indeterminate until the next address access. Write Mode The bq4845 is in write mode whenever WE and CS are active. The start of a write is referenced from the latter-occurring falling edge of WE or CS. A write is ter- minated by the earlier rising edge of WE or CS. The ad- dresses must be held valid throughout the cycle. CS or WE must return high for a minimum of tWR2 from CS or tWR1 from WE prior to the initiation of another read or write cycle. Data-in must be valid tDW prior to the end of write and remain valid for tDH1 or tDH2 afterward. OE should be kept high during write cycles to avoid bus contention; al- though, if the output bus has been activated by a low on CS and OE, a low on WE disables the outputs tWZ after WE falls. Reading the Clock Once every second, the user-accessible clock/calendar lo- cations are updated simultaneously from the internal real time counters. To prevent reading data in transi- tion, updates to the bq4845 clock registers should be halted. Updating is halted by setting the update trans- fer inhibit (UTI) bit D3 of the control register E. As long as the UTI bit is 1, updates to user-accessible clock loca- tions are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory loca- tions, the UTI bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the UTI bit, reading the clock locations has no effect on clock ac- curacy. Once the UTI bit is reset to 0, the internal regis- ters update within one second the user-accessible regis- ters with the correct time. A halt command issued dur- ing a clock update allows the update to occur before freezing the data. Setting the Clock The UTI bit must also be used to set the bq4845 clock. Once set, the locations can be written with the desired information in BCD format. Resetting the UTI bit to 0 causes the written values to be transferred to the inter- nal clock counters and allows updates to the user- accessible registers to resume within one second. Stopping and Starting the Clock Oscillator The bq4845 clock can be programmed to turn off when the part goes into battery back-up mode by setting STOP to 0 prior to power down. If the board using the bq4845 is to spend a significant period of time in stor- age, the STOP bit can be used to preserve some battery capacity. STOP set to 1 keeps the clock running when VCC drops below VSO. With VCC greater than VSO, the bq4845 clock runs regardless of the state of STOP. Power-Down/Power-Up Cycle The bq4845 continuously monitors VCC for out-of- tolerance. During a power failure, when VCC falls below VPFD, the bq4845 write-protects the clock and storage registers. When VCC is below VBC (3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VBC, the power source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD. An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq4845. As the voltage input VCC slews down during a power failure, the chip enable output, CEOUT, is forced inactive independent of the chip enable input CEIN. 5 Bits Description 24/12 24- or 12-hour representation ABE Alarm interrupt enable in battery-backup mode AF Alarm interrupt flag AIE Alarm interrupt enable ALM0–ALM1 Alarm mask bits BVF Battery-valid flag DSE Daylight savings time enable PF Periodic interrupt flag PIE Periodic interrupt enable PM/AM PM or AM indication PWRF Power-fail interrupt flag PWRIE Power-fail interrupt enable RS0–RS3 Periodic interrupt rate STOP Oscillator stop and start UTI Update transfer inhibit WD0 - WD2 Watchdog time-out rate Table 2. Clock and Control Register Bits Aug. 1995 bq4845/bq4845Y |
Similar Part No. - BQ4845YS-A4G4 |
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Similar Description - BQ4845YS-A4G4 |
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