POR

No

Yes

InitializeDACOutput

LoadDACwithAll0s

EEPROM

Download

TheBUF12840

EntersSlaveMode

Set

EN=1

BUF12840

SBOS519A

– OCTOBER 2010 – REVISED JULY 2011

www.ti.com

EEPROM ADDRESS SELECT PINS

mode operation is needed, EN should be tied to

DVSS; it is recommended that after POR occurs wait

EA0 and EA1 are used to select the proper EEPROM

at least 15ms before addressing the BUF12840.

size. Table 4 shows the start and stop address to

Figure 12 shows how EN affects the operation of the

load each of the DAC registers. The state of the

BUF12840 in a typical application.

select pins must be set before the auto read function

is activated.

The BUF12840 tries to read up to 10 times spaced

1ms apart during POR, which can occur if the

Enable Pin

EEPROM is not ready or if the two-wire bus is kept

busy by another device. By the end of the tenth

The

status

of

EN

at

power-on

reset

(POR)

attempt, if the download cannot be started, the

determines the modes of operation of the BUF12840,

BUF12840 goes into slave mode. This action ensures

as described in Table 3. If EN = 1, the BUF12840

that the BUF12840 enters slave mode within 25ms

acts as a master; after the data download finishes,

from the POR condition, regardless if the download is

the BUF12840 enters slave mode. If EN = 0, the

successful or not.

BUF12840 skips the master mode and enters slave

mode directly. Once in slave mode after POR,

changing the status of EN has no effect on the

BUF12840

unless

the

user

issues

a

GCR

(general-call reset) or RA (read again) command.

Table 3. EN Modes of Operation

EEPROM AUTO

ENABLE EN

LOGIC LEVEL

READ

Low

0

Disabled

High

1

Enabled

After a POR condition is detected by the BUF12840,

a 10ms window occurs. As long as EN goes high in

this window, the BUF12840 downloads data from the

EEPROM. It is recommended that this pin be tied to

DVDD if the application allows. However, if only slave

Figure 12. Effect of EN in a Typical Set Up

Table 4. EEPROM Configuration

REGISTER BANK0

REGISTER BANK1

START WORD

END WORD

START WORD

END WORD

ACCEPTABLE

EA0

EA1

ADDRESS

ADDRESS

ADDRESS

ADDRESS

0

0

0

23

24

47

1k, 2k, 4k, 8k, 16k

0

1

361

384

405

428

2k, 4k, 8k, 16k

32k, 64k, 128k, 256k

1

0

0

23

24

47

and larger

32k, 64k, 128k, 256k

1

1

361

384

405

428

and larger

(1)

Any applicable EEPROM chip select pins (A2, A1, A0) must be hardwired to GND.

(2)

When EA0 = 0 and EA1 = 1, it is required that the types of EEPROM that supports Page/Block address definition with chip select pins

(for example, A0 is part of the Word Address).

10

Copyright

© 2010–2011, Texas Instruments Incorporated