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AD9289BBC-65EB Datasheet(PDF) 1 Page - Analog Devices |
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AD9289BBC-65EB Datasheet(HTML) 1 Page - Analog Devices |
1 / 16 page Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter Preliminary Technical Data AD9289 FEATURES • Four ADCs in one package • Serial LVDS digital output data rates up to 520 Mbps (ANSI- 644) • Data clock output provided • SNR = 47 dB (to Nyquist) • Excellent Linearity: DNL = ±0.25 LSB (Typical) INL = ±0.5 LSB (Typical) • 400 MHz full power analog bandwidth • Power dissipation = 112 mW Core ADC Power per channel at 65 MSPS • 1 Vpp – 2 Vpp input voltage range • +3.0 V supply operation • Power down mode APPLICATIONS • Tape drives • Medical imaging PRODUCT DESCRIPTION The AD9289 is a quad 8-bit, 65 MSPS analog–to–digital converter with an on–chip track–and–hold circuit and is designed for low cost, low power, small size and ease of use. The product operates up to 65 MSPS conversion rate and is optimized for outstanding dynamic performance where a small package size is critical. The ADC requires a single+3V power supply and an LVDS compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. A separate output power supply pin supports LVDS compatible serial digital output levels. The ADC automatically multiplies up the sample rate clock for the appropriate LVDS serial data rate. An FCO trigger is provided to signal a new output byte. Power down is supported, and the ADC consumes less than 10mW when enabled. Fabricated on an advanced CMOS process, the AD9289 is available in a 64-ball mini-BGA package (64 CSP_BGA) specified over the industrial temperature range (–40°C to +85°C). FUNCTIONAL BLOCK DIAGRAM Serial LVDS Pipeline ADC SHA Data Rate Multiplier Ref Select + - 0.5 V Serial LVDS Pipeline ADC SHA AD9289 D1+A D1-A D1+D D1-D CLK+ CLK- AGND VREF SENSE VIN+A VIN-A VIN+D VIN-D AVDD DRVDD 8 8 PDWN DCO+ DCO- REFT_B REFB_B FCO+ FCO- OR+ OR- S1 DRGND SHARED_REF CML REFT_A REFB_A LVDSBIAS LOCK Figure 1. Functional Block Diagram PRODUCT HIGHLIGHTS 1. Four analog-to-digital converters are contained in one small, space saving package. 2. A Data Clock Out (DCO) is provided which operates up to 260 MHz. 3. The outputs of each ADC are serialized and provided on the rising and falling edge of DCO). Output data rates up to 520 Mbps (8 bits x 65 MSPS) are available. 4. The AD9289 operates from a single 3V power supply. 5. The clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles AD9289 R1 2.3MHz Typical at Nominal Conditions, 2VFS Int Ref SNR = 49.1dB, SFDR = 71.9dB -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 5 10 15 20 25 30 Figure 2. Measured FFT Rev. PrJ 6/25/2004 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved. |
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