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AD9860PCB Datasheet(PDF) 4 Page - Analog Devices |
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AD9860PCB Datasheet(HTML) 4 Page - Analog Devices |
4 / 32 page REV. 0 –4– AD9860/AD9862 Test AD9860/AD9862 (20 pF Load) Temp Level Min Typ Max Unit Minimum Reset Pulsewidth Low (tRL)NA NA 5 Clock Cycles Digital Output Rise/Fall Time 25ºC III 2.8 4 ns DLL Output Clock 25ºC III 32 128 MHz DLL Output Duty Cycle 25ºC III 50 % Tx–/Rx–Interface (See Figures 11 and 12) TxSYNC/TxIQ Setup Time (tTx1, tTx3)25ºC III 3 ns TxSYNC/TxIQ Hold Time (tTx2, tTx4)25ºC III 3 ns RxSYNC/RxIQ/IF to Valid Time(tRx1, tRx3)25ºC III 5.2 ns RxSYNC/RxIQ/IF Hold Time (tRx2, tRx4)25ºC III 0.2 ns Serial Control Bus (See Figures 1 and 2) Maximum SCLK Frequency (fSCLK) Full III 16 MHz Minimum Clock Pulsewidth High (tHI) Full III 30 ns Minimum Clock Pulsewidth Low (tLOW) Full III 30 ns Maximum Clock Rise/Fall Time Full III 1 ms Minimum Data/SEN Setup Time (tS) Full III 25 ns Minimum SEN/Data Hold Time (tH) Full III 0 ns Minimum Data/SCLK Setup Time (tDS) Full III 25 ns Minimum Data Hold Time (tDH) Full III 0 ns Output Data Valid/SCLK Time (tDV) Full III 30 ns AUXILARY ADC Conversion Rate 25ºC III 1.25 MHz Input Range 25ºC III 3 V Resolution 25ºC III 10 Bits AUXILARY DAC Settling Time 25ºC III 8 ms Output Range 25ºC III 3 V Resolution 25ºC III 8 Bits ADC TIMING Latency (All Digital Processing Blocks Disabled) 25ºC III 7 Cycles DAC Timing Latency (All Digital Processing Blocks Disabled) 25ºC III 3 Cycles Latency (2 Interpolation Enabled) 25ºC III 30 Cycles Latency (4 Interpolation Enabled) 25ºC III 72 Cycles Additional Latency (Hilbert Filter Enabled) 25ºC III 36 Cycles Additional Latency (Coarse Modulation Enabled) 25ºC III 5 Cycles Additional Latency (Fine Modulation Enabled) 25ºC III 8 Cycles Output Settling Time (TST) (to 0.1%) 25ºC III 35 ns Specifications subject to change without notice. TIMING CHARACTERISTICS Test AD9860/AD9862 PARAMETERS (continued) Temp Level Min Typ Max Unit POWER SUPPLY (continued) Rx Path (fADC = 64 MSPS) Processing Blocks Disabled 25ºC III 9 mA Decimation Filter Enabled 25ºC III 15 mA Hilbert Filter Enabled 25ºC III 16 mA Hilbert and Decimation Filter Enabled 25ºC III 18.5 mA NOTES 1% f DATA refers to the input data rate of the digital block. 2Interpolation filter stop band is defined by image suppression of 50 dB or greater. Specifications subject to change without notice. |
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Similar Description - AD9860PCB |
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