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DP83901 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DP83901 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 62 page  Pin Description (Continued) Pin No Pin Name IO Description BUS INTERFACE PINS (Continued) 39 PRQADS1 O Z PORT REQUESTADDRESS STROBE 1 32-BIT MODE If LAS is set in the Data Configuration Register this line is programmed as ADS1 It is used to strobe addresses A16 – A31 into external latches (A16 – A31 are the fixed addresses stored in RSAR0 RSAR1) ADS1 will remain at TRI-STATE until BACK is received 16-BIT MODE If LAS is not set in the Data Configuration Register this line is programmed as PRQ and is used for Remote DMA Transfers The SNIC initiates a single remote DMA read or write operation by asserting this pin In this mode PRQ will be a standard logic output Note This line will power up as TRI-STATE until the Data Configuration Register is programmed 40 BACK I BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that the CPU has granted the bus to the SNIC If immediate bus access is desired BREQ should be tied to BACK Tying BACK to VCC will result in a deadlock 41 BREQ O BUS REQUEST Bus Request is an active high signal used to request the bus for DMA transfers This signal is automatically generated when the FIFO needs servicing 65 RESET I RESET Reset is active low and places the SNIC in a reset immediately no packets are transmitted or received by the SNIC until STA bit is set Affects Command Register Interrupt Mask Register Data Configuration Register and Transmit Configuration Register The SNIC will execute reset within 10 BSCK cycles and TXC cycles 67 INT O INTERRUPT Indicates that the SNIC requires CPU attention after reception transmission or completion of DMA transfers The interrupt is cleared by writing to the ISR (Interrupt Service Register) All interrupts are maskable 68 WACK I WRITE ACKNOWLEDGE Issued from system to SNIC to indicate that data has been written to the external latch The SNIC will begin a write cycle to place the data in local memory NETWORK INTERFACE PINS 42 TXb O TRANSMIT OUTPUT Differential driver which sends the encoded data to the transceiver The outputs are source followers which require 270X pulldown resistors 43 TXa 46 TEST I FACTORY TEST INPUT Used to check the chip’s internal functions Tied low during normal operation 47 SEL I MODE SELECT When high Transmita and Transmitb are the same voltage in the idle state When low Transmita is positive with respect to Transmitb in the idle state at the transformer’s primary 50 X1 I EXTERNAL OSCILLATOR INPUT 51 GNDX2 O GROUNDX2 This in should normally be connected to ground It is possible to use a crystal oscillator using X1 and GNDX2 if certain precautions are taken Contact National Semiconductor for more information 56 SNISEL I FACTORY TEST INPUT For normal operation tied to VCC When low enables the ENDEC module to be tested independently of the SNIC module 60 RXb I RECEIVE INPUT Differential receive input pair from the transceiver 61 RXa 62 CDb I COLLISION INPUT Differential collision pair input from the transceiver 63 CDa 4 |
Similar Part No. - DP83901 |
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Similar Description - DP83901 |
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