DS26LV32AT

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SNLS128C – APRIL 1999 – REVISED FEBRUARY 2013

DS26LV32AT 3V Enhanced CMOS Quad Differential Line Receiver

Check for Samples: DS26LV32AT

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FEATURES

•

Available in SOIC and CLGA Packaging

•

Standard Microcircuit Drawing (SMD) 5962-

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•

Low Power CMOS Design (30 mW typical)

98585

•

Interoperable with Existing 5V RS-422

Networks

DESCRIPTION

•

Industrial and Military Temperature Range

The DS26LV32A is a high speed quad differential

•

Conforms to TIA/EIA-422-B (RS-422) and ITU-T

CMOS receiver that meets the requirements of both

V.11 Recommendation

TIA/EIA-422-B

and

ITU-T

V.11.

The

CMOS

•

3.3V Operation

which makes it ideal for battery powered and power

•

conscious applications. The TRI-STATE enables, EN

•

and EN*, allow the device to be active High or active

Low. The enables are common to all four receivers.

•

Receiver OPEN Input Failsafe Feature

•

Guaranteed AC Parameter:

The receiver output (RO) is guaranteed to be High

when the inputs are left open. The receiver can

–

Maximum Receiver Skew:

4 ns

detect signals as low as ±200 mV over the common

–

Maximum Transition Time:

10 ns

mode range of ±10V. The receiver outputs (RO) are

•

Pin Compatible with DS26C32AT

compatible with TTL and LVCMOS levels.

•

32 MHz Toggle Frequency

•

> 6.5k ESD Tolerance (HBM)

Connection Diagram

Top View

Figure 1.

SOIC Package

See Package Numbers D0016A or NAD0016A

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PRODUCTION DATA information is current as of publication date.

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Products conform to specifications per the terms of the Texas

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