DS32EL0124, DS32ELX0124

www.ti.com

SNLS284K – MAY 2008 – REVISED APRIL 2013

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS

Parallel Interface

Check for Samples: DS32EL0124, DS32ELX0124

1

FEATURES

KEY SPECIFICATIONS

2

•

5-bit DDR LVDS Parallel Data Interface

•

1.25 to 3.125 Gbps Serial Data Rate

•

Programmable Receive Equalization

•

125 to 312.5 MHz DDR Parallel Clock

•

Selectable DC-Balance Decoder

•

-40° to +85°C Temperature Range

•

Selectable De-Scrambler

•

> 8 kV ESD (HBM) Protection

•

Remote Sense for Automatic Detection and

•

0.5 UI Minimum Input Jitter Tolerance (1.25

Negotiation of Link Status

Gbps)

•

No External Receiver Reference Clock

DESCRIPTION

Required

The DS32EL0124/DS32ELX0124 integrates clock

•

LVDS Parallel Interface

and data recovery modules for high-speed serial

•

Programmable LVDS Output Clock Delay

communication

over

FR-4

printed

circuit

board

•

Supports Output Data-Valid Signaling

backplanes, balanced cables, and optical fiber. This

easy-to-use chipset integrates advanced signal and

•

Supports Keep-Alive Clock Output

clock conditioning functions, with an FPGA friendly

•

On Chip LC VCOs

interface.

•

Redundant Serial Input (ELX device only)

The DS32EL0124/DS32ELX0124 deserializes up to

•

Retimed Serial Output (ELX device only)

3.125 Gbps of high speed serial data to 5 LVDS

•

Configurable PLL Loop Bandwidth

outputs without the need for an external reference

clock.

With

DC-balance

decoding

enabled,

the

•

Configurable via SMBus

application payload of 2.5 Gbps is deserialized to 4

•

Loss of Lock and Error Reporting

LVDS outputs.

•

48-pin WQFN Package with Exposed DAP

The

DS32EL0124/DS32ELX01214

deserializers

feature a remote sense capability to automatically

APPLICATIONS

signal

link

status

conditions

to

its

companion

•

Imaging: Industrial, Medical Security, Printers

DS32EL0421/ELX0421 serializers without requiring

an additional feedback path.

•

Displays: LED Walls, Commercial

The parallel LVDS interface of these devices reduce

•

Video Transport

FPGA I/O pins, board trace count and alleviates EMI

•

Communication Systems

issues, when compared to traditional single-ended

•

Test and Measurement

wide bus interfaces.

•

Industrial Bus

The DS32EL0124/ELX0124 is programmable through

a SMBus interface as well as through control pins.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.