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ADF7020BCP Datasheet(PDF) 7 Page - Analog Devices |
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ADF7020BCP Datasheet(HTML) 7 Page - Analog Devices |
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7 / 40 page  Preliminary Technical Data ADF7020 Rev. PrH | Page 7 of 40 TIMING CHARACTERISTICS VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, but not production tested. Table 2. Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments t1 <10 ns SDATA to SCLK Setup Time t2 <10 ns SDATA to SCLK Hold Time t3 <25 ns SCLK High Duration t4 <25 ns SCLK Low Duration t5 <10 ns SCLK to SLE Setup Time t6 <20 ns SLE Pulse Width t7 <TBD ns SLE to SCLK Setup Time, Readback t8 <TBD ns SCLK to SREAD Data Valid, Readback t9 <TBD ns SREAD Hold Time after SCLK, Readback t10 <TBD ns SCLK to SLE Disable Time, Readback SCLK SLE DB31 (MSB) DB30 DB2 DB1 (CONTROL BIT C2) SDATA DB0 (LSB) (CONTROL BIT C1) t6 t1 t2 t3 t4 t5 Figure 2. Serial Interface Timing Diagram t8 t3 t1 t2 t10 t9 X RV16 RV15 RV2 RV1 SCLK SDATA SLE SREAD REG7 DB0 (CONTROL BIT C1) Figure 3. Readback Timing Diagram |
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