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FDC1004QDGSRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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FDC1004QDGSRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 29 page  SCL tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr tBUF SDA FDC1004Q SNOSCZ4 – APRIL 2015 www.ti.com 7.7 I 2C Interface Timing Over recommended operating free-air temperature range, VDD = 3.3 V, for TA = TJ = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Clock frequency(1) 10 400 kHz tLOW Clock low time(1) 1.3 µs tHIGH Clock high time(1) 0.6 µs tHD;STA Hold time (repeated) START After this period, the first clock pulse 0.6 µs condition(1) is generated tSU;STA Set-up time for a repeated START 0.6 µs condition(1) tHD;DAT Data hold time(1)(2) 0 ns tSU;DAT Data setup time(1) 100 ns tf SDA fall time(1) IL ≤ 3mA; CL ≤ 400pF 300 ns tSU;STO Set-up time for STOP condition (1) 0.6 µs tBUF Bus free time between a STOP and 1.3 µs START condition(1) tVD;DAT Data valid time(1) 0.9 ns tVD;ACK Data valid acknowledge time(1) 0.9 ns tSP Pulse width of spikes that must be 50 ns suppressed by the input filter(1) (1) This parameter is specified by design and/or characterization and is not tested in production. (2) The FDC1004Q provides an internal 300 ns minimum hold time to bridge the undefined region of the falling edge of SCL. Figure 1. I2C Timing 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: FDC1004Q |
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