ADS5203

SBAS258A – JUNE 2002 – REVISED JULY 2002

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5

PIN CONFIGURATION

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

DRVDD

1,13

I

Supply Voltage for Output Drivers

DRVSS

12, 24

I

Digital Ground for Output Drivers

DA 9..0

14-23

O

Data Outputs for Bus A. D9 is MSB. This is the primary bus. Data from both input channels can be output on this bus

or data from the A channel only. Pins SELB and MODE select the output mode. The data outputs are in tri-state during

power-down (refer to Timing Options table).

DB 9..0

2-11

O

Data Outputs for Bus B. D9 is MSB. This is the second bus. Data is output from the B-channel when dual bus output mode

is selected. The data outputs are in tri-state during power-down and single-bus modes (refer to Timing Options table).

OE

48

I

Output Enable. A LOW on this terminal will enable the data output bus, COUT and COUT.

COUT

26

O

Latch Clock for the Data Outputs. COUT is in tri-state during power-down.

COUT

25

O

Inverted Latch Clock or multiplexer control for the Data Outputs. COUT is in tri-state during power–down.

SELB

44

I

Selects either single-bus data output or dual-bus data output. A LOW selects dual-bus data output.

DVSS

43

I

Digital Ground

CLK

47

I

Clock Input. The input is sampled on each rising edge of CLK when using a 40MHz input and alternate rising edges when

using an 80MHz input. The clock pin is referenced to AVDD and AVSS to reduce noise coupling from digital logic.

DVDD

45

I

Digital Supply Voltage

AVDD

27,37,41

I

Analog Supply Voltage

MODE

46

I

Selects the COUT and COUT output mode.

AVSS

28,36,40

I

Analog Ground

B–

35

I

Negative Input for the Analog B Channel

B+

34

I

Positive Input for the Analog B Channel

REFT

31

I/O

Reference Voltage Top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering

should be applied to this input: the use of 0.1

µF capacitor between REFT and AVSS is recommended. Additionally a 0.1µF

capacitor should be connected between REFT and REFB.

REFB

30

I/O

Reference Voltage Bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient

filtering should be applied to this input: the use of 0.1

µF capacitor between REFB and AVSS is recommended. Additionally

a 0.1

µF capacitor should be connected between REFT and REFB.

CML

32

O

Common-Mode Level. This voltage is equal to (AVDD – AVSS)/2. An external capacitor of 0.1µF should be connected

between this terminal and AVSS when CML is used as a bias voltage. No capacitor is required if CML is not used.

PDWN_REF

33

I

Power-Down for Internal Reference Voltages. A HIGH on this terminal disables the internal reference circuit.

STBY

42

I

Standby Input. A HIGH on this terminal will power down the device.

A–

39

I

Negative Input for the Analog A Channel

A+

38

I

Positive Input for Analog A Channel

TP

29

This pin must be connected to DVDD. It should not be left floating.