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ADSP-BF533SBBC500 Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-BF533SBBC500 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 56 page  ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. 0 | Page 7 of 56 | March 2004 interrupt events by writing the appropriate values into the Inter- rupt Assignment Registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC. Event Control The ADSP-BF531/2/3 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC Interrupt Latch Register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. • CEC Interrupt Mask Register (IMASK) – The IMASK reg- ister controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, pre- venting the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) • CEC Interrupt Pending Register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7. • SIC Interrupt Mask Register (SIC_IMASK)– This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servic- ing the event. • SIC Interrupt Status Register (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. • SIC Interrupt Wakeup Enable Register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor- mation, see Dynamic Power Management on Page 11.) Table 2. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0 Emulation/Test Control EMU 1 Reset RST 2Non-Maskable Interrupt NMI 3Exception EVX 4 Reserved 5 Hardware Error IVHW 6Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 Table 3. System Interrupt Controller (SIC) Peripheral Interrupt Event Default Mapping PLL Wakeup IVG7 DMA Error IVG7 PPI Error IVG7 SPORT 0 Error IVG7 SPORT 1 Error IVG7 SPI Error IVG7 UART Error IVG7 Real-Time Clock IVG8 DMA Channel 0 (PPI) IVG8 DMA Channel 1 (SPORT 0 RX) IVG9 DMA Channel 2 (SPORT 0 TX) IVG9 DMA Channel 3 (SPORT 1 RX) IVG9 DMA Channel 4 (SPORT 1 TX) IVG9 DMA Channel 5 (SPI) IVG10 DMA Channel 6 (UART RX) IVG10 DMA Channel 7 (UART TX) IVG10 Timer 0 IVG11 Timer 1 IVG11 Timer 2 IVG11 PF Interrupt A IVG12 PF Interrupt B IVG12 DMA Channels 8 and 9 (Memory DMA Stream 1) IVG13 DMA Channels 10 and 11 (Memory DMA Stream 0) IVG13 Software Watchdog Timer IVG13 |
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