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DP8391AN Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP8391AN Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 12 page  80 Switching Characteristics VCC e 5V g5% TA e 0 Cto70 C for DIP and 0 Cto55 C for PCC (Note 2) (Continued) Symbol Parameter Figure Min Typ Max Units TRANSMIT SPECIFICATION (Continued) tTOd Transmit Output Delay from Transmit Clock Rising Edge 4 12 50 ns tTOr Transmit Output Rise Time (20% to 80%) 12 7 ns tTOf Transmit Output Fall Time (80% to 20%) 12 7 ns tTOj Transmit Output Jitter 12 g 025 ns tTOh Transmit Output High Before Idle in Half Step Mode 5 12 200 ns tTOi Transmit Output Idle Time in Half Step Mode 5 12 800 ns RECEIVE SPECIFICATION tRCd Receive Clock Duty Cycle at 50% (10 MHz) 12 40 50 60 % tRCr Receive Clock Rise Time (20% to 80%) 12 8 ns tRCf Receive Clock Fall Time (80% to 20%) 12 8 ns tRDr Receive Data Rise Time (20% to 80%) 12 8 ns tRDf Receive Data Fall Time (80% to 20%) 12 8 ns tRDs Receive Data Stable from Receive Clock Rising Edge 7 12 g 40 ns tCSon Carrier Sense Turn On Delay 7 12 50 ns tCSoff Carrier Sense Turn Off Delay 8 912 160 ns tDAT Decoder Acquisition Time 7 06 180 m s tDrej Differential Inputs Rejection Pulse Width (Squelch) 7 5 30 ns tRd Receive Throughput Delay 8 12 150 ns COLLISION SPECIFICATION tCOLon Collision Turn On Delay 10 12 50 ns tCOLoff Collision Turn Off Delay 10 12 350 ns LOOPBACK SPECIFICATION tLBs Loopback Setup Time 11 20 ns tLBh Loopback Hold Time 11 0 ns Note 2 All typicals are given for VCC e 5V and TA e 25 C 90 Timing and Load Diagrams TLF9357 – 6 FIGURE 4 Transmit Timing - Start of Transmission 7 |
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