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AK4525 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4525 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
10 / 18 page ASAHI KASEI [AK4525] MS0053-E-00 2000/9 - 10 - n Audio Serial Interface Format Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The AK4525 supports the master mode. In this case, SCLK and LRCK are outputs and the frequency of SCLK is fixed to 64fs. Four serial data modes selected by the DIF0 and DIF1 pins are supported as shown in Table 3. In all modes the serial data has MSB first, 2’s compliment format. The data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least significant bits will be truncated. Mode DIF1 DIF0 SDTO (ADC) SDTI (DAC) L/R SCLK (Slave) 0 0 0 20bit, MSB justified 16bit, LSB justified H/L ≥ 32fs 1 0 1 20bit, MSB justified 20bit, LSB justified H/L ≥ 40fs 2 1 0 20bit, MSB justified 20bit, MSB justified H/L ≥ 40fs 3 1 1 IIS (I2S) IIS (I2S) L/H 32fs or ≥ 40fs Table 2. Serial Data Modes Note: In master mode, SCLK frequency is fixed to 64fs. LRCK(i) SCLK(i:64fs) SDTO(o) 01 2 19 17 18 20 31 0 1 2 19 17 18 20 31 0 19 1 18 0 19 18 3 2 0 19 SDTI(i) 1 14 0 12 11 1 14 0 12 11 SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB Lch Data Rch Data Don’t Care Don’t Care 32 SCLK(i:32fs) SDTO(o) 0 1 2 9 10 12 13 15 0 1 2 9 10 12 13 15 0 19 1 18 8 19 18 8 11 10 19 SDTI(i) 1 60 43 1 15 0 54 11 10 2 54 76 17 15 14 13 311 14 9 5 7 17 1 13 15 30 17 33 17 14 13 76 3 2 15 14 11 4 5 6 7 9 1 15 13 2 2 Figure 2. Mode 0 Timing LRCK(i) SCLK(i:64fs) SDTO(o) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 19 1 18 0 19 18 8 7 6 0 19 SDTI(i) 1 18 0 19 12 11 1 18 0 19 12 11 19:MSB, 0:LSB Lch Data Rch Data Don’t Care Don’t Care 876 Figure 3. Mode 1 Timing |
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