ASAHI KASEI

[AK4565]

MS0132-E-01

2003/05

- 11 -

OPERATION OVERVIEW

n System Clock Input

The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs

∼). The master clock (MCLK) should

be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be input as

256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.

*fs is sampling frequency.

All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC or DAC is in operation. If

these clocks are not provided, the AK4565 may draw excess current and will not operate properly because it utilizes these

clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4565 should be placed in

power-down mode.

n System Reset

The AK4565 is placed in the power-down mode by bringing PDN “L”. This reset should always be done after power-up.

After the system reset operation, the all internal registers are initial value.

Initialization cycle is 4128/fs=86ms@fs=48kHz. During initializing cycle, the ADC digital data outputs of both channels

are forced to a 2’s compliment “0”. Output data of ADC settles data equivalent for analog input signal after initializing

cycle. This cycle is not for DAC.

Writing to Addr = 01H must not be done during initialization cycle after exiting power-down mode by

PDN pin. If the writing to 01H is done, a normal initialization cycle may not be done.