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AK5365VQ Datasheet(PDF) 5 Page - Asahi Kasei Microsystems |
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AK5365VQ Datasheet(HTML) 5 Page - Asahi Kasei Microsystems |
5 / 41 page ASAHI KASEI [AK5365] MS0164-E-01 2002/08 - 5 - No. Pin Name I/O Function 23 LRCK I/O Output Channel Clock Pin 24 MCLK I Master Clock Input Pin 25 PDN I Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initializes the control register. 26 ALC I ALC Enable Pin (Internal Pull-down Pin, typ. 100k Ω) “H” : ALC Enable, “L” : ALC Disable 27 SMUTE I Soft Mute Pin (Internal Pull-down Pin, typ. 100k Ω) “H” : Soft Mute, “L” : Normal Operation 28 SEL0 I Input Selector 0 Pin 29 SEL1 I Input Selector 1 Pin 30 SEL2 I Input Selector 2 Pin CDTI I Control Data Input Pin in 3-wire Control (CTRL pin = “L”) 31 SDA I/O Control Data Input / Output Pin in I 2C Control (CTRL pin = “H”) CCLK I Control Data Clock Pin in 3-wire Control (CTRL pin = “L”) 32 SCL I Control Data Clock Pin in I 2C Control (CTRL pin = “H”) CSN I Chip Select Pin in 3-wire Control (CTRL pin = “L”) 33 CAD1 I Chip Address 1 Select Pin in I 2C Control (CTRL pin = “H”) 34 CTRL I Control Mode Pin “H” : I 2C Control & I2S Compatible, “L” : 3-wire Control 35 M/S I Master / Slave Mode Pin “H” : Master Mode, “L” : Slave Mode 36 RIN1 I Rch Analog Input 1 Pin 37 TEST5 I Test 5 Pin (Connected to AVSS) 38 RIN2 I Rch Analog Input 2 Pin 39 TEST6 I Test 6 Pin (Connected to AVSS) 40 RIN3 I Rch Analog Input 3 Pin 41 TEST7 I Test 7 Pin (Connected to AVSS) 42 RIN4 I Rch Analog Input 4 Pin 43 TEST8 I Test 8 Pin (Connected to AVSS) 44 RIN5 I Rch Analog Input 5 Pin Note: All digital input pins except pull-down pins should not be left floating. Note: TEST5, TEST6, TEST7 and TEST8 pins should be connected to AVSS. |
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