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AT49LH004-33TC Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT49LH004-33TC Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 36 page  9 AT49LH004 3383B–FLASH–9/03 Figure 2. FWH Read Cycle Note: 1. Field contents are valid on the rising edge of the present clock cycle. CLK FWH4/LFRAME FWH/LAD[3:0] 1101b IDSEL A15-A12 A27-A24 A23-A20 A19-A16 A11-A8 A7-A4 A3-A0 0000b High-Z 0101b 0101b 0000b D3-D0 D7-D4 1111b High-Z 1111b 12 6 3 4 5 7 8 9 10 12 13 14 15 16 17 18 19 11 START IDSEL MADDR MSIZE TAR1 WSYNC WSYNC RSYNC DATA DATA TAR0 TAR1 TAR0 Table 4. FWH Read Cycle Clock Cycle Field Name Field Value (1) FWH/LAD[3:0] FWH/LAD[3:0] Direction Comments 1 START 1101b IN FWH4/LFRAME must be active (low) for the device to respond. Only the last START field (before FWH4/LFRAME transitioning high) should be recognized. The START field contents indicate a FWH memory read cycle. 2 IDSEL 0000b to 1111b IN Indicates which FWH memory device should respond. If the IDSEL field matches the strapping values on ID[3:0], then that particular device will respond to subsequent commands. 3 - 9 MADDR YYYY IN These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred with the most significant nibble first. 10 MSIZE 0000b (indicates 1byte) IN The MSIZE field indicates how many bytes will be transferred. The device only supports single-byte operations, so MSIZE must be 0000b. 11 TAR0 1111b IN then float In this clock cycle, the master has driven the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turn-around cycle”. 12 TAR1 1111b (float) Float then OUT The device takes control of the bus during this clock cycle. 13 - 14 WSYNC 0101b (wait) OUT The device outputs the value 0101b, a “wait” SYNC, for two clock cycles. This value indicates to the master that data is not yet available from the device. This number of wait-syncs is a function of the device’s memory access time. 15 RSYNC 0000b (ready) OUT During this clock cycle, the device will generate a “ready” SYNC indicating that the least significant nibble of the data byte will be available during the next clock cycle. 16 DATA YYYY OUT YYYY is the least significant nibble of the data byte. 17 DATA YYYY OUT YYYY is the most significant nibble of the data byte. 18 TAR0 1111b OUT then float The FWH memory device drives the bus to 1111b to indicate a turn-around cycle. 19 TAR1 1111b (float) Float then IN The FWH memory device floats its outputs, and the master regains control of the bus during this clock cycle. |
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Similar Description - AT49LH004-33TC |
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