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AT49LH004-33TC Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT49LH004-33TC Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 36 page  11 AT49LH004 3383B–FLASH–9/03 LPC Memory Cycles A valid LPC memory cycle begins with the host driving the FWH4/LFRAME signal low for one or more clock cycles. While the FWH4/LFRAME signal is low, a valid START value of 0000b must be driven on the FWH/LAD[3:0] pins. Following the START field, a CYCTYPE + DIR (Cycle Type and Direction) field must be sent to the device to indicate the type of cycle (e.g., memory access, I/O access, etc.) and the direction (read or write) of the transfer. After the CYCTYPE + DIR field has been sent, the 8-clock MADDR (Memory Address) field must be sent to the device to provide the 32-bit starting address location of where to begin reading or writing in the memory. Figure 4. LPC Memory Cycle Initiation and Addressing START FIELD: This 1-clock field indicates the start of a cycle. It is valid on the last clock that FWH4/LFRAME is sampled low. The start field that is used for an LPC cycle is 0000b. If the start field that is sampled is not 0000b, then the cycle attempted is not an LPC memory cycle. It may be a valid FWH memory cycle that the device will attempt to decode. CYCTYPE + DIR (CYCLE TYPE AND DIRECTION) FIELD: This 1-clock field is used to indi- cate the type of cycle and the direction of the transfer to be performed. Of the four bits placed on the FWH/LAD[3:0] pins, bits[3:2] must be 01b to indicate that the transfer will be a memory cycle. Values other than 01b, which may be used to specify an I/O cycle or a DMA cycle for other components in the system, will cause the device to enter standby mode when the FWH4/LFRAME pin is brought high and no internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high-impedance state. Bit[1] is used to determine the direction of the transfer. 0 is used to indicate a read, and 1 is used to indicate a write. Bit[0] is ignored and reserved for future use. Table 6 details the two valid CYCTYPE + DIR fields that the device will respond to. MADDR (MEMORY ADDRESS) FIELD: This is an 8-clock field that is used to provide a 32-bit (A31 - A0) memory address. The 32 address bits allow for the provisioning to access up to 4 GB of memory space. The AT49LH004 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A31 - A24. Address bit A23 is used to determine whether reads or writes to the device will be directed to the memory array (A23 = 1) or to the register space (A23 = 0). Unlike FWH memory cycles, LPC cycles do not use an IDSEL field to determine which LPC device in the system is being selected. Instead, the strapping values on the ID[3:0] pins are compared against address bits A22 - A19 in the MADDR field. For the actual comparison, the strapped values are internally inverted. For example, if ID3 was strapped to GND, a logical value of 1 would be compared against address bit A22. If the inverted states of the ID[3:0] pins match with address bits A22 - A19, then the device will continue to decode the rest of cycle (see LPC Multiple Device Selection for mode details). Addresses are transferred to the device with the most significant nibble first. Table 6. Valid CYCTYPE + DIR Values FWH/LAD[3:0] Cycle Type 010xb LPC Memory Read 011xb LPC Memory Write CLK FWH4/LFRAME FWH/LAD[3:0] START MADDR MADDR MADDR MADDR MADDR MADDR MADDR MADDR CYCTYPE + DIR |
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