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SCAN92LV090 Datasheet(PDF) 5 Page - Texas Instruments

Part # SCAN92LV090
Description  SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SCAN92LV090 Datasheet(HTML) 5 Page - Texas Instruments

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SCAN92LV090
www.ti.com
SNLS058I – SEPTEMBER 2000 – REVISED APRIL 2013
DC ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified
(1)(2)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
IIL
Input Low Current
VIN = GND
TCK
-20
+20
µA
ICCD
Power Supply Current Drivers
No Load, DE = RE = VCC,
VCC
50
80
mA
Enabled, Receivers Disabled
DIN = VCC or GND
ICCR
Power Supply Current Drivers
DE = RE = 0V, VID = ±300mV
50
80
mA
Disabled, Receivers Enabled
ICCZ
Power Supply Current, Drivers
DE = 0V; RE = VCC,
50
80
mA
and Receivers tri-state
DIN = VCC or GND
ICC
Power Supply Current, Drivers
DE = VCC; RE = 0V,
and Receivers Enabled
DIN = VCC or GND,
160
210
mA
RL = 27Ω
ICCS
Power Supply Current (SCAN
DE = VCC; RE = 0V,
Test Mode), Drivers and
DIN = VCC or GND,
180
230
mA
Receivers Enabled
RL = 27Ω, TAP in any state other
than Test-Logic-Reset
IOFF
Power Off Leakage Current
VCC = 0V or OPEN,
DO+/RI+,
DIN, DE, RE = 0V or OPEN,
DO
−/RI−
−20
+20
µA
VAPPLIED = 3.6V (Port Pins)
COUTPUT
Capacitance @ Bus Pins
DO+/RI+,
5
pF
DO
−/RI−
COUTPUT
Capacitance @ ROUT
ROUT
7
pF
AC ELECTRICAL CHARACTERISTICS
Over recommended operating supply voltage and temperature ranges unless otherwise specified
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD
Differential Prop. Delay High to Low (2)
RL = 27Ω,
1.0
1.8
2.6
ns
See Figure 5 and
tPLHD
Differential Prop. Delay Low to High (2)
1.0
1.8
2.6
ns
Figure 6
tSKD1
Differential Skew |tPHLD–tPLHD|
(3)
120
ps
CL = 10 pF
tSKD2
Chip to Chip Skew (4)
1.6
ns
tSKD3
Channel to Channel Skew (5)
0.25
0.55
ns
tTLH
Transition Time Low to High
0.5
1.2
ns
tTHL
Transition Time High to Low
0.5
1.2
ns
tPHZ
Disable Time High to Z
RL = 27Ω,
3
8
ns
See Figure 7 and
tPLZ
Disable Time Low to Z
3
8
ns
Figure 8
tPZH
Enable Time Z to High
3
8
ns
CL = 10 pF
tPZL
Enable Time Z to Low
3
8
ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD
Differential Prop. Delay High to Low (2)
See Figure 9 and
2.0
2.4
3.9
ns
Figure 10
tPLHD
Differential Prop Delay Low to High (2)
2.0
2.4
3.9
ns
CL = 35 pF
tSDK1
Differential Skew |tPHLD–tPLHD|
(3)
210
ps
tSDK2
Chip to Chip Skew (4)
1.9
ns
tSDK3
Channel to Channel skew (5)
0.35
0.7
ns
tTLH
Transition Time Low to High
1.5
2.5
ns
tTHL
Transition Time High to Low
1.5
2.5
ns
(1)
Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2)
Propagation delays are specified by design and characterization.
(3)
tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions.
(4)
Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
(5)
Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device,
common edge.
Copyright © 2000–2013, Texas Instruments Incorporated
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