SCAN921023, SCAN921224

SNLS133D – JAN 2001 – REVISED APRIL 2013

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When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the

embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise

ROUT0–ROUT9 is invalid.

The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled

by the RCLK_R/F input. See Figure 15.

ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 66

MHz clock.

Resynchronization

When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the

Deserializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter TRI-STATE.

The user's system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can

arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches

are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync

request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop

application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are

critical. However, the Deserializer can lock to random data, which is discussed in the next section.

Random Lock Initialization and Resynchronization

The initialization and resynchronization methods described in their respective sections are the fastest ways to

establish the link between the Serializer and Deserializer. However, the SCAN921224 can attain lock to a data

stream without requiring the Serializer to send special SYNC patterns. This allows the SCAN921224 to operate

in “open-loop” applications. Equally important is the Deserializer's ability to support hot insertion into a running

backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore,

because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time.

However, please see Table 1 for some general random lock times under specific conditions. The primary

constraint on the “random” lock time is the initial phase relation between the incoming data and the REFCLK

when the Deserializer powers up. As described in the next paragraph, the data contained in the data stream can

also affect lock time.

If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as

the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than

one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN

9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the

Deserializer could become locked to the data pattern rather than the clock. Circuitry within the SCAN921224 can

detect that the possibility of “false lock” exists. The circuitry accomplishes this by detecting more than one

potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming

active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will

eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock

bits in the serial data stream. Graphical representations of RMT are shown in Figure 1. Please note that RMT

only applies to bits DIN0-DIN8.

Powerdown

When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the

Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown

when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In

Powerdown, the PLL stops and the outputs enterTRI-STATE, which disables load current and reduces supply

current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high.

Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the

devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and

assert LOCK high until lock to the Bus LVDS clock occurs.

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