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MAX3232CDWR Datasheet(PDF) 11 Page - Texas Instruments |
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MAX3232CDWR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 27 page ±9 ±8 ±7 ±6 ±5 ±4 ±3 ±2 ±1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 Time (s) DIN DOUT to RIN ROUT C001 MAX3232 www.ti.com SLLS410K – JANUARY 2000 – REVISED JANUARY 2015 Standard Application (continued) 10.2.1 Design Requirements • Recommended VCC is 3.3 V or 5 V. 3 V to 5.5 V is also possible • Maximum recommended bit rate is 250 kbit/s. 10.2.2 Detailed Design Procedure • All DIN, FORCEOFF and FORCEON inputs must be connected to valid low or high logic levels. • Select capacitor values based on VCC level for best performance. 10.2.3 Application Curves Figure 7. 250 kbit/s Driver to Receiver Loopback Timing Waveform, VCC= 3.3 V 11 Power Supply Recommendations VCC should be between 3 V and 5.5 V. Charge pump capacitors should be chosen using table in Figure 6. Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: MAX3232 |
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