 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SCANSTA101 Datasheet(PDF) 6 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
SCANSTA101 Datasheet(HTML) 6 Page - Texas Instruments |
|
|
6 / 39 page  SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Max Units IOFF Power Off Leakage Current VCC = 0.0V 5.0 μA All pins except TDI, TMS, TRST, and TDI_SM ICC Maximum Quiescent Supply Current 250 μA ICCmax Maximum Supply Current All inputs low 1.2 mA ICCT Maximum ICC/Input VIN = VCC − 0.6V 250 μA AC ELECTRICAL CHARACTERISTICS/OPERATING REQUIREMENTS Over recommended operating supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω unless otherwise specified. Symbol Parameter Conditions # of SCK Min Max Units (1) (2) PARALLEL PROCESSOR INTERFACE (PPI) tS1 Set Up Time See Figure 12 and Figure 13 0 ns CE, R/W, Addr, Data to STB tH1 Hold Time See Figure 12 and Figure 13 0 ns CE, R/W, Addr, Data to DTACK tD1 Propagation Delay See Figure 12 2 or 3 11.5 ns STB low to DTACK low, Register Write tD1 Propagation Delay See Figure 13 4 or 5 11.5 ns STB low to DTACK low, Register Read tD1 Propagation Delay STB low to DTACK low, Memory Write: See Figure 12 3 or 4 11.5 ns 16-bit first access tD1 Propagation Delay STB low to DTACK low, Memory Write: See Figure 12 7 or 8 11.5 ns 16-bit second access tD1 Propagation Delay STB low to DTACK low, Memory Read: See Figure 13 9 or 10 11.5 ns 16-bit first access tD1 Propagation Delay STB low to DTACK low, Memory Read: See Figure 13 3 or 4 11.5 ns 16-bit second access tD2 Propagation Delay STB high to DTACK TRISTATE, Register See Figure 12 1 or 2 10.0 ns Write tD2 Propagation Delay STB high to DTACK TRISTATE, Register See Figure 13 1 or 2 10.0 ns Read tD2 Propagation Delay STB high to DTACK TRISTATE, Memory See Figure 12 1 or 2 10.0 ns Write: 16-bit first access tD2 Propagation Delay STB high to DTACK TRISTATE, Memory See Figure 12 1 or 2 10.0 ns Write: 16-bit second access tD2 Propagation Delay STB high to DTACK TRISTATE, Memory See Figure 13 1 or 2 10.0 ns Read: 16-bit first access tD2 Propagation Delay STB high to DTACK TRISTATE, Memory See Figure 13 1 or 2 10.0 ns Read: 16-bit second access (1) Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle. (2) An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + tD.For example, for tD1 (STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, tD, is 11.5ns. For a SCK with a 100ns period, the absolute maximum delay is (3 x 100ns) + 11.5, or 311.5ns. 6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: SCANSTA101 |
Similar Part No. - SCANSTA101 |
|
Similar Description - SCANSTA101 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
