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TMS370C090AFNT Datasheet(PDF) 7 Page - Texas Instruments |
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TMS370C090AFNT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 55 page  TMS370Cx9x 8-BIT MICROCONTROLLER SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CPU (continued) The ’x9x CPU architecture provides the following components: D CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global-interrupt-enable bits – A program counter (PC) that points to the memory location of the next instruction to be executed D A memory map that includes : – 128 bytes of general-purpose RAM that can be data memory storage, program instructions, general-purpose register, or the stack (can be located only in the first 128 bytes) – A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control – A 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off conditions – 4K bytes of ROM or 8K bytes of EPROM program memory stack pointer (SP) The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. The stack is used typically to store the return address on subroutine calls as well as the status register contents during interrupt sequences. The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed onto the stack and decrements after data is popped from the stack. The stack can be located only in the first 128 bytes of the on-chip RAM memory. status register (ST) The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits: D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional jump instructions) use these status bits to determine program flow. D The two interrupt-enable bits control the two interrupt levels. The ST register and status bit notation are shown in Table 3. Table 3. Status Register 7 6 5 4 3 2 1 0 C N Z V IE2 IE1 Reserved Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read, W = write, 0 = value after reset |
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