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AT91RM3400-AI-001 Datasheet(PDF) 7 Page - ATMEL Corporation

Part # AT91RM3400-AI-001
Description  ARM7TDMI??based Microcontroller
Download  461 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT91RM3400-AI-001 Datasheet(HTML) 7 Page - ATMEL Corporation

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AT91RM3400
1790A–ATARM–11/03
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
Support for Two PDC Channels with Connection to Receiver and Transmitter
Debug Communication Channel Support
Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor
Interrupt Generation
Chip ID Registers
Identification of the Device Revision, Sizes of the Embedded Memories, Set
of Peripherals
ICE Access Prevention
Enables Software to Prevent System Access Through the ARM Processor’s ICE
Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE
Parallel Input/Output
Controller
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Two Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose
I/O)
Input Change Interrupt
Glitch Filter
Multi-drive Option Enables Driving in Open Drain
Programmable Pull Up on Each I/O Line
Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any
Time
Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
Serial Peripheral
Interface
Supports Communication with Serial External Devices
4 Chip Selects with External Decoder Support Allow Communication with Up
to 15 Peripherals
Serial Memories, such as DataFlash and 3-wire EEPROMs
Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers
and Sensors
External Co-processors
Master or Slave Serial Peripheral Bus Interface
8- to 16-bit Programmable Data Length Per Chip Select
Programmable Phase and Polarity Per Chip Select
Programmable Transfer Delays Between Consecutive Transfers and
Between Clock and Data Per Chip Select
Programmable Delay Between Consecutive Transfers
Selectable Mode Fault Detection
Connection to PDC Channel Capabilities Optimizes Data Transfers
One Channel for the Receiver, One Channel for the Transmitter
Next Buffer Support


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