SN54ALS133, SN74ALS133

13-INPUT POSITIVE-NAND GATES

SDAS202B – APRIL 1982 – REVISED DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These devices contain a 13-input positive-NAND

gate.

They

perform

the

following

Boolean

functions in positive logic:

Y=A

•B•C•D•E•F•G•H•I•J•K•L•M

Y=A +B +C +D +E +F +G +H +I +J +K +L +M

The SN54ALS133 is characterized for operation

over the full military temperature range of – 55

°C

to 125

°C. The SN74ALS133 is characterized for

operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS A – M

OUTPUT

Y

All inputs H

L

One or more inputs L

H

logic diagram (positive logic)

&

Y

9

1

A

2

B

3

C

4

D

5

E

13

K

14

L

15

M

6

F

7

G

10

H

11

I

12

J

Y

9

1

A

2

B

3

C

4

D

5

E

13

K

14

L

15

M

6

F

7

G

10

H

11

I

12

J

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS133 ...J PACKAGE

SN74ALS133 ...D OR N PACKAGE

(TOP VIEW)

SN54ALS133 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A

B

C

D

E

F

G

GND

M

L

K

J

I

H

Y

32 1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

L

K

NC

J

I

C

D

NC

E

F

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.