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BCM4356XKUBGT Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # BCM4356XKUBGT
Description  Single-Chip 5G WiFi IEEE 802.11ac 2횞2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

BCM4356XKUBGT Datasheet(HTML) 10 Page - Cypress Semiconductor

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Table of Contents
BCM4356 Advance Data Sheet
Broadcom®
May 8, 2015 • 4356-DS103-R
Page 9
BROADCOM CONFIDENTIAL
Section 18: Internal Regulator Electrical Specifications ............................................. 160
Core Buck Switching Regulator.............................................................................................................. 160
3.3V LDO (LDO3P3) .................................................................................................................................. 161
3.3V LDO (LDO3P3_B).............................................................................................................................. 162
2.5V LDO (BTLDO2P5) ............................................................................................................................. 163
CLDO ......................................................................................................................................................... 164
LNLDO ....................................................................................................................................................... 165
Section 19: System Power Consumption...................................................................... 166
WLAN Current Consumption................................................................................................................... 166
Bluetooth and FM Current Consumption ............................................................................................... 168
Section 20: Interface Timing and AC Characteristics .................................................. 169
SDIO Timing.............................................................................................................................................. 169
SDIO Default Mode Timing ................................................................................................................. 169
SDIO High-Speed Mode Timing.......................................................................................................... 171
SDIO Bus Timing Specifications in SDR Modes ................................................................................. 172
Clock Timing ................................................................................................................................ 172
Device Input Timing ..................................................................................................................... 173
Device Output Timing................................................................................................................... 174
SDIO Bus Timing Specifications in DDR50 Mode............................................................................... 177
Data Timing, DDR50 Mode .......................................................................................................... 178
PCI Express Interface Parameters .......................................................................................................... 179
JTAG Timing ............................................................................................................................................. 181
Section 21: Power-Up Sequence and Timing ............................................................... 182
Sequencing of Reset and Regulator Control Signals ........................................................................... 182
Description of Control Signals ............................................................................................................. 182
Control Signal Timing Diagrams.......................................................................................................... 183
Power-up Sequences .......................................................................................................................... 185
Section 22: Package Information ................................................................................... 187
Package Thermal Characteristics ........................................................................................................... 187
Junction Temperature Estimation and PSIJT Versus ThetaJC.............................................................. 188
Environmental Characteristics................................................................................................................ 188
Section 23: Mechanical Information .............................................................................. 189
Section 24: Ordering Information .................................................................................. 193


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