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AT94K40AL-25BQI Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT94K40AL-25BQI Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 192 page  1 Features • Monolithic Field Programmable System Level Integrated Circuit (FPSLIC™) – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR ® Core, Extensive Data and Instruction SRAM and JTAG ICE • 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™ – 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM – High-performance DSP Optimized FPGA Core Cell – Dynamically Reconfigurable In-System – FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Logic ® Designs – Very Low Static and Dynamic Power Consumption – Ideal for Portable and Handheld Applications • Patented AVR Enhanced RISC Architecture – 120+ Powerful Instructions – Most Single Clock Cycle Execution – High-performance Hardware Multiplier for DSP-based Systems – Approaching 1 MIPS per MHz Performance – C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers – Low-power Idle, Power-save and Power-down Modes – 100 µA Standby and Typical 2-3 mA per MHz Active • Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM – Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM – Upto16Kbytesx 8Internal 15 ns DataSRAM • JTAG (IEEE std. 1149.1 Compliant) Interface – Extensive On-chip Debug Support – Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports) • AVR Fixed Peripherals – Industry-standard 2-wire Serial Interface – Two Programmable Serial UARTs – Two 8-bit Timer/Counters with Separate Prescaler and PWM – One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM • Support for FPGA Custom Peripherals – AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible to FPGA – FPGA Macro Library of Custom Peripherals • 16 FPGA Supplied Internal Interrupts to AVR • Up to Four External Interrupts to AVR • 8 Global FPGA Clocks – Two FPGA Clocks Driven from AVR Logic – FPGA Global Clock Access Available from FPGA Core • Multiple Oscillator Circuits – Programmable Watchdog Timer with On-chip Oscillator – Oscillator to AVR Internal Clock Circuit – Software-selectable Clock Frequency – Oscillator to Timer/Counter for Real-time Clock • V CC: 3.0V - 3.6V • 3.3V 33 MHz PCI-compliant FPGA I/O – 20 mA Sink/Source High-performance I/O Structures – All FPGA I/O Individually Programmable • High-performance, Low-power 0.35µ CMOS Five-layer Metal Process • State-of-the-art Integrated PC-based Software Suite including Co-verification • 5V I/O Tolerant 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE AT94K Series Field Programmable System Level Integrated Circuit Rev. 1138F–FPSLI–06/02 |
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