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SN54HC191-DIE

SCLS748 – MARCH 2014

SN54HC191-DIE 4-Bit Synchronous Up/Down Binary Counter

1

1 Features

These counters feature a fully independent clock

•

Wide Operating Voltage Range

circuit. Change at the control (CTEN and D/U) inputs

•

Low Power Consumption

that modifies the operating mode have no effect on

•

Low Input Current

the contents of the counter until clocking occurs. The

•

Single Down/Up Count-Control Line

function of the counter is dictated solely by the

condition meeting the stable setup and hold times.

•

Look-Ahead Circuitry Enhances Speed of

Cascaded Counters

These counters are fully programmable; that is, each

of the outputs can be preset to either level by placing

•

Fully Synchronous in Count Modes

a low on the load (LOAD) input and entering the

•

Asynchronously Presettable With Load Control

desired data at the data inputs. The output changes

to agree with the data inputs independently of the

2 Description

level of CLK. This feature allows the counters to be

The

SN54HC191-DIE

is

a

4-bit

synchronous,

used as modulo-N dividers simply by modifying the

reversible, up/down binary counter. Synchronous

count length with the preset inputs.

counting operation is provided by having all flip-flops

Two outputs are available to perform the cascading

clocked simultaneously so that the outputs change

function: ripple clock (RCO) and maximum/minimum

coincident with each other when instructed by the

(MAX/MIN) count. MAX/MIN produces a high-level

steering logic. This mode of operation eliminates the

output pulse with a duration approximately equal to

output counting spikes normally associated with

one complete cycle of the clock while the count is

asynchronous (ripple-clock) counters.

zero (all outputs low) counting down, or maximum (9

The outputs of the four flip-flops are triggered on a

or 15) counting up. RCO produces a low-level output

low- to high-level transition of the clock (CLK) input if

pulse under those same conditions, but only while

the count-enable (CTEN) input is low. A high at

CLK is low. The counters can be cascaded easily by

CTEN inhibits counting. The direction of the count is

feeding RCO to CTEN of the succeeding counter if

determined by the level of the down/up (D/U) input.

parallel clocking is used, or to CLK if parallel enabling

When D/U is low, the counter counts up, and when

is used. MAX/MIN can be used to accomplish look

D/U is high, it counts down.

ahead for high-speed operation.

PACKAGE

PRODUCT

PACKAGE

ORDERABLE PART NUMBER

PACKAGE QUANTITY

DESIGNATOR

SN54HC191TDE1

154

SN54HC191

TD

SN54HC191TDE2

10

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Processing is per the Texas Instruments space production baseline and is in compliance with the Texas Instruments Quality Control

System in effect at the time of manufacture. Electrical screening consists of DC parametric and functional testing at room temperature

only. Unless otherwise specified by Texas Instruments AC performance and performance over temperature is not warranted. Visual

Inspection is performed in accordance with MIL-STD-883 Test Method 2010 Condition B at 75X minimum.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.